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Interface IP

DDR3 PHY

The Rambus DDR3 memory PHY is optimized for applications requiring reduced system cost, improved performance and faster time-to-market. With the Northwest Logic DDR3 Controller it comprises a complete DDR3 memory interface subsystem.

How the DDR3 Interface works

The Rambus DDR3 memory PHY is fully compatible with DDR3 at 1.5V and DDR3L at 1.35V and scalable to 2133Mbps. The PHY has undergone extensive design-phase modeling and simulation of alternative SOC, package and PCB environments to ease implementation and enable first-time-right designs.

The Northwest Logic DDR3 controller maximizes memory bus efficiency via Look-Ahead command processing, bank management, auto-precharge and additive latency support. The core is DFI compatible and supports a range of interfaces to user logic.

DDR3 Memory Interface Subsystem
DDR3 Memory Interface Subsystem

The Rambus DDR3 PHY and Northwest Logic DDR3 controller used together comprise a complete DDR3 memory interface subsystem. Alternatively, these cores can be licensed separately to be paired with 3rd-party DDR3 controller or PHY solutions.

Solution Offerings

2.5D/3D Packaging Solutions for AI and HPC

Memory Systems for AI and Leading-Edge Applications

Thanks to rapid advancements in computing, neural networks are fueling tremendous growth in AI for a broad spectrum of applications. Learn about the memory architectures, and their relative advantages, at the heart of the AI revolution.

Protocol Compatibility

ProtocolData Rate (Gbps) Application
DDR3 (1.5V)1600-2133IoT, Edge
DDR3L (1.35V)1600-1866IoT, Edge

Inventions

FlexPhase™ Timing Adjustment Circuits

FlexPhase per bit timing adjustment circuits deskew data and clock signals to improve signal integrity and simplify package and PCB system design.

Output Driver Calibration

Output driver calibration allows SoC designers to tune the output signaling to optimal levels in order to improve data rates and system voltage margin.

On Die Termination Calibration

ODT calibration enables higher data rates and superior DRAM device and module performance by establishing the optimal termination value to compensate for variations in process and operating conditions that degrade signal performance.