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Interface IP

DDR3 PHY

With short design windows and heightened sensitivity to costs, consumer electronics need low-risk solutions that deliver enhanced flexibility and reduced time-to-market. Designed for ease-of-integration and optimized for consumer applications, our silicon-proven DDR3 PHY delivers improved performance and margin with support for low cost packaging and board design options.

How DDR3 works

The Rambus DDR3 memory PHY is optimized for consumer applications with reduced system cost, improved performance and faster time-to-market. Fully compatible with DDR3 at 1.5V and DDR3L at 1.35V and scalable to 2133Mbps, the PHY has undergone extensive design-phase modeling and simulation of alternative SOC, package and PCB environments to ease implementation and enable first-time-right designs. In order to deliver improved flexibility of design, the R+ DDR3 PHY supports wire-bond (running up to 1600 Mbps) and flip-chip (running up to 2133 Mbps) packaging options and is compatible with 4- and 6-layer PCB designs. In addition, it features FlexPhase™ circuits that enable Per byte timing adjustment circuits deskew data and clock signals to improve signal integrity and simplify package and PCB system design.

The DDR3 PHY is fully characterized and is available in 28LP process.

DDR3 PHY subsystem example

DDR3 Subsystem Example

Solution Offerings

  • PLL-based clocking with internal clock alignment to the parallel clock on the memory controller interface
  • Autonomous initialization
  • Support for multiple channel configurations from x16 through x72 per channel
  • Support for multiple DRAM widths (x4, x8, x16, x32)
  • Support for single channel, 1 to 4 ranks
  • Excepteur sint occaecat cupidatat non proident,
  • Selectable low-power operating states
  • DFI 3.1 compliant for easy integration with memory controller
  • Programmable output impedance and on-die termination
  • ZQ calibration of output impedance and on-die calibration
  • Utilizes standard 8-layer 6020 metal layer stack.
  • Supports C4 flip-chip packaging options
  • Register interface for state observation
  • Test traffic generation and error checking for in-situ test
  • LabStation™ software environment for system level bring-up, characterization, and validation
  • Fully-characterized hard macro (GDSII):
  • Complete design views:
    • Gate-level and IO models
    • Verification test benches
    • Layout abstracts (.lef)
    • Timing models (.lib)
  • Memory controller reference design
  • Full Documentation
    • Integration Guidelines
    • Package and PCB design guidelines
    • ASIC/DFT manufacturing guidelines
    • Test and Characterization user guide
    • Verilog models
    • CDL netlists *(.cdl)
    • ATPG models
    • GDSII layout
    • DRC & LVS reports

Comprehensive Chip and System Design Reviews

  • Kickoff/Program Review
  • Floor plan Review
  • Test/Characterization Plan Review
  • Package Design Review
  • Board Design Review
  • Final Chip Integration Review
  • Bring-up and Test Review
 

Engineering Design Services:

  • Package design
  • System board layout
  • Statistically-based signal and power integrity analysis

Protocol Compatibility

ProtocolData Rate (Gbps) Application
DDR3 (1.5V)1600-2133Consumer Electronics
DDR3L (1.35V)1600-1866Consumer Electronics

Inventions

FlexPhase™ Timing Adjustment Circuits

FlexPhase per bit timing adjustment circuits deskew data and clock signals to improve signal integrity and simplify package and PCB system design.

Output Driver Calibration

Output driver calibration allows SoC designers to tune the output signaling to optimal levels in order to improve data rates and system voltage margin.

On Die Termination Calibration

ODT calibration enables higher data rates and superior DRAM device and module performance by establishing the optimal termination value to compensate for variations in process and operating conditions that degrade signal performance.

Related Markets & Applications

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