The Rambus DDR4 memory PHY delivers industry-leading data rates of up to 3200 Mbps and is compatible with JEDEC standard DDR4, and DDR3. Designed to meet the needs of the most demanding networking and data center applications, the silicon-proven PHY combines performance and power efficiency with superior design flexibility to provide customers with a differentiated and easy to integrate solution.
The PHY consists of a Command/Address (C/A) macro cell and Data (DQ) macro cells configured to create a 72 bits wide channel.
DDR4 PHY Subsystem Example
Comprehensive Chip and System Design Reviews
Engineering Design Services:
|Protocol||Data Rate (Gbps)||Application|
|DDR4||1600-3200||Data Center and Networking|
|DDR3 (1.5V)||1066-2133||Data Center and Networking|
|DDR3L (1.35V)||1066-2133||Data Center and Networking|
|DDR3U (1.25V)||1066-2133||Data Center and Networking|
ODT calibration enables higher data rates and superior DRAM device and module performance by establishing the optimal termination value to compensate for variations in process and operating conditions that degrade signal performance.
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