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Interface IP


Designed to meet the memory-intensive workload demands of networking and data center applications, the DDR4 memory PHY delivers maximum performance and power efficiency while maintaining full compatibility with industry standard DDR4 and DDR3.

How DDR4 works

The Rambus DDR4 memory PHY delivers industry-leading data rates of up to 3200 Mbps and is compatible with JEDEC standard DDR4, and DDR3. Designed to meet the needs of the most demanding networking and data center applications, the silicon-proven PHY combines performance and power efficiency with superior design flexibility to provide customers with a differentiated and easy to integrate solution.

The PHY consists of a Command/Address (C/A) macro cell and Data (DQ) macro cells configured to create a 72 bits wide channel.

DDR4 PHY Subsystem Example

Solution Offerings

  • Autonomous initialization (PHY independent mode)
  • Support for multiple channel configurations from x16 through x72 per channel
  • Support for single channel, 1up to 4 ranks
  • Selectable low-power operating states
  • DFI 4.0 and 3.1 compliant for easy integration with memory controller
  • Programmable output impedance and on-die termination
  • Available in North-South, East-West, and Corner configurations
  • ZQ calibration of output impedance and on-die calibration
  • Utilizes standard 8-layer 602011- or 13- metal layer stack.
  • Supports package-on-package and C4 flip-chip packaging options
  • Register interface for state observation
  • Test traffic generation and error checking for in-situ test
  • LabStation™ software environment for system level bring-up, characterization, and validation
  • Fully-characterized hard macro (GDSII):
  • North-South side of SOC Placement
  • Complete design views:
    • Gate-level and IO models
    • Verification test benches
    • Layout abstracts (.lef)
    • Timing models (.lib)
  • Memory controller reference design
  • Full Documentation
    • Integration Guidelines
    • Package and PCB design guidelines
    • ASIC/DFT manufacturing guidelines
    • Test and Characterization user guide
    • Verilog models
    • CDL netlists *(.cdl)
    • ATPG models
    • GDSII layout
    • DRC & LVS reports

Comprehensive Chip and System Design Reviews

  • Kickoff/Program Review
  • Floor plan Review
  • Test/Characterization Plan Review
  • Package Design Review
  • Board Design Review
  • Final Chip Integration Review
  • Bring-up and Test Review

Engineering Design Services:

  • Package design
  • System board layout
  • Statistically-based signal and power integrity analysis

Protocol Compatibility

ProtocolData Rate (Gbps) Application
DDR41600-3200Data Center and Networking
DDR3 (1.5V)1066-2133Data Center and Networking
DDR3L (1.35V)1066-2133Data Center and Networking
DDR3U (1.25V)1066-2133Data Center and Networking


FlexPhase™ Timing Adjustment Circuits

FlexPhase per bit timing adjustment circuits deskew data and clock signals to improve signal integrity and simplify package and PCB system design.

Output Driver Calibration

Output driver calibration allows SoC designers to tune the output signaling to optimal levels in order to improve data rates and system voltage margin.

On Die Termination Calibration

ODT calibration enables higher data rates and superior DRAM device and module performance by establishing the optimal termination value to compensate for variations in process and operating conditions that degrade signal performance.

Related Markets & Applications

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