The Rambus DDR4 memory PHY delivers industry-leading data rates of up to 3200 Mbps and is compatible with the DDR4 and DDR3 standards. The PHY consists of a Command/Address (C/A) macro cell and Data (DQ) macro cells configured to create a 72-bit wide channel.
The Rambus DDR4 controller maximizes memory bus efficiency via Look-Ahead command processing, bank management, auto-precharge and additive latency support. The core is DFI compatible and supports a range of interfaces to user logic.
The Rambus DDR4 PHY and DDR4 controller used together comprise a complete DDR4 memory interface subsystem. Alternatively, these cores can be licensed separately to be paired with 3rd-party DDR4 controller or PHY solutions.
|Protocol||Data Rate (Gbps)||Application|
|DDR4||1600-3200||Data Center and Networking|
|DDR3 (1.5V)||1066-2133||Data Center and Networking|
|DDR3L (1.35V)||1066-2133||Data Center and Networking|
|DDR3U (1.25V)||1066-2133||Data Center and Networking|
ODT calibration enables higher data rates and superior DRAM device and module performance by establishing the optimal termination value to compensate for variations in process and operating conditions that degrade signal performance.