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Interface IP

GDDR6 PHY

Designed for performance and power efficiency, the GDDR6 PHY enables big data analytics, crypto mining, ADAS, AI, machine learning, and deep learning.

How GDDR6 PHY works

The Rambus GDDR6 (Graphics Double Data Rate) Memory PHY enables the communication to and from high-speed, high-bandwidth GDDR6 SGRAM (Synchronous Graphics Random Access) memory. Originally designed for graphics applications, GDDR6 is a high-performance memory solution that can be used in a variety of high-performance applications that require large amounts of data computation like artificial intelligence (AI), crypto mining, deep learning, autonomous vehicles, and high-speed networking.
GDDR6 PHY Subsystem Example

GDDR6 PHY Subsystem Example

The Rambus GDDR6 PHY will be fully compliant to the JEDEC GDDR6 (JESD250) standard, supporting up to 16 Gbps per pin, and is available on TSMC 7nm process. The GDDR6 interface supports 2 channels, each with 16 bits for a total data width of 32 bits. With Speeds up to 16 Gbps per pin the Rambus GDDR6 PHY will offer a maximum bandwidth of up to 64 GB/s. This PHY will be available in advanced FinFET nodes for leading-edge customer integration. The Rambus system-aware design methodology used for IP Cores delivers a customer focused experience with improved time-to-market and first-time-right quality. Rambus offers flexible delivery of IP cores and will work directly with the customer to provide a full system signal and power integrity analysis, creating an optimized chip layout. In the end, the customer receives a hard macro solution with a full suite of test software for quick turn-on, characterization and debug.

Going Beyond GPUs with GDDR6

Going Beyond GPUs with GDDR6

Supported by Micron Technology, SK Hynix and Samsung, GDDR6 SGRAM will feature a maximum data transfer rate of 16 Gbps, along with an operating voltage of 1.35V. GDDR6 offers higher densities compared to previous-generation graphics memory. In addition, GDDR6 doubles the speed (12–16 Gb/s) of GDDR5 and provides more than 5X the 3.2 Gb/s speed of DDR4. Although initially targeted at game consoles and PC graphics, the latest iteration of GDDR is expected to be deployed across multiple verticals, with Micron specifically highlighting the data center and automotive sector.

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Solution Offerings

  • JESD250 Compliant
  • Available on TSMC 7nm process
  • Flexible delivery of IP core: works with ASIC/ SoC layout requirements
  • Speed bins: 12 Gbps, 14 Gbps, 16 Gbps
  • 2 Channels
  • Support for GDDR6 SGRAM
  • DFI 3.1 style interface for easy integration with memory controller
  • Memory controller or PHY can be ASIC interface master (PHY independent mode)
  • Selectable low-power operating states
  • Programmable Driver/Termination impedance value
  • Driver/Termination Impedance calibration
  • In-built test support
  • Utilizes 13-layer metal stack
  • Register interface for state observation
  • LabStation™ software environment for system level bring-up, characterization, and validation
  • Fully-characterized hard macro (GDSII)
  • Complete design views:
    • Gate-level and IO models
    • Layout abstracts (.lef)
    • Timing models (.lib)
    • Verilog Behavior model
    • CDL netlists (.cdl)
    • GDSII layout
    • DRC & LVS reports
  • Full documentation:
    • Datasheet
    • Package design guidelines
    • ASIC/DFT manufacturing guidelines
    • Test and characterization user guide

Comprehensive Chip and System Design Reviews

  • Kickoff/Program Review
  • Floor plan Review
  • Test/Characterization Plan Review
  • Package Design Review
  • Board Design Review
  • Final Chip Integration Review
  • Bring-up and Test Review
 

Engineering Design Services:

  • Package design
  • System board layout
  • Statistically-based signal and power integrity analysis
The Rambus GDDR6 PHY IP Core thumbnail

The Rambus GDDR6 PHY IP Core

The JEDEC-compliant Rambus GDDR6 PHY IP Core is optimized for systems that require low-latency and high-bandwidth GDDR6 memory solutions. Available on leading FinFET process nodes, the PHY interface supports two independent channels, with each supporting 16 bits for a total data width of 32 bits. In addition, the PHY supports speeds up to 16Gbps per pin, providing a maximum bandwidth of up to 64 GB/s.
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