Memory + Interfaces

DDR4 Multi-modal PHY

Designed for server, networking, computing and consumer applications, our DDR4 multi-modal memory PHY is optimized for performance and power efficiency while maintaining full compatibility with industry standard DDR4, DDR3, LPDDR3, and LPDDR2 interfaces. This broad compatibility, combined with support for a wide range of data rates, delivers our customers superior design flexibility and ease of integration.


Product Brief

How DDR4 Multi-modal PHY works

The DDR4 multi-modal PHY is a DFI 3.1 compliant memory interface that supports both UDIMM and RDIMM modules as well as DRAM–on-motherboard topologies, making it suitable for a broad range of enterprise and consumer applications.

Our silicon-proven PHY consists of a Command/Address (C/A) block, Clock and Power Management block and Data (DQ) macro cells to create a 72 bits wide channel. It is fully characterized and contains all of the necessary components for robust operation and is available in GF 28SLP and SS 28 LPP processes.

The PHY has also undergone extensive design-phase modeling and simulation to ease implementation.

R+ DDR4 Multi-modal PHY block diagram

DDR4 Multi-modal Subsystem Example

Solution Offerings

Protocol Compatibility

ProtocolData Rate (Gbps)Application
DDR3 (1.5V)800-2133Consumer Electronics
DDR3L (1.35V)800-1866Consumer Electronics
DDR3U (1.25V)800-1866Low-Power Consumer Electronics


FlexPhase™ Timing Adjustment Circuits


FlexPhase per bit timing adjustment circuits deskew data and clock signals to improve signal integrity and simplify package and PCB system design.

Output Driver Calibration

Output driver calibration allows SoC designers to tune the output signaling to optimal levels in order to improve data rates and system voltage margin.

On Die Termination (ODT) Calibration


ODT calibration enables higher data rates and superior DRAM device and module performance by establishing the optimal termination value to compensate for variations in process and operating conditions that degrade signal performance.

From the blog

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Data Center