Memory + Interfaces

HBM Gen2 PHY

Optimized for the low-latency and high-bandwidth memory applications, the HBM Gen2 PHY delivers maximum performance and flexibility in minimal form factor and power envelope.

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Product Brief

HBM Gen2 Subsystem Example

HBM Gen 2 PHY Subsystem Example

How it works

HBM is a high-performance memory that features reduced power consumption and a small form factor.  It combines 2.5D packaging with a wider interface at a lower clock speed (as compared to DDR4) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for high-performance computing applications.

The Rambus HBM Gen2 PHY is fully compliant to the JEDEC HBM2 standard and supports data rates up to 2000 Mbps per data pin, resulting in a total bandwidth of 256 GB/s. The interface features 8 independent channels, each containing 128 bits for a total data width of 1024 bits, and support for a stack height of 2, 4 or 8 DRAMs. In addition, the PHY is designed for a 2.5D system with an interposer for routing signals between the DRAM and PHY. This combination of signal density and stacked form factor requires special design consideration. In order to enable easy implementation and improved flexibility of design in such a complex system, Rambus performs complete signal and power integrity analysis on the entire 2.5D system to ensure that all signal, power and thermal requirements are met.

Solution Offerings

Protocol Compatibility

Protocol Data Rate (Gbps) Application
HBM2 0.5-2000 Data Center and Networking

Inventions

Phase Interpolator-based CDR

Phase-Interpolator-based-Clock-and-Data-Recovery-CDR-thumbnail

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.

Related Markets & Applications

Data Center