DDR5 Registering Clock Driver (DDR5 RCD)

The Rambus Registering Clock Driver (DDR5 RCD) chips enable DDR5 Registered DIMMs (RDIMMs) operating up to 9600 MT/s. 

DescriptionPart NumberProduct BriefApplications
9600 MT/s Registering Clock DriverDR5RCD6GxxDownload DDR5 RCD 9600 MT/s Product BriefServer RDIMM
8000 MT/s Registering Clock DriverDR5RCD5GxxDownload DDR5 RCD 8000 MT/s Product BriefServer RDIMM
7200 MT/s Registering Clock DriverRCD4-GXXDownload DDR5 RCD 7200 MT/s Product BriefServer RDIMM
6400 MT/s Registering Clock DriverRCD3-GXXDownload DDR5 RCD 6400 MT/s Product BriefServer RDIMM
5600 MT/s Registering Clock DriverRCD2-GXXDownload RCD 5600 Product BriefServer RDIMM
4800 MT/s Registering Clock DriverRCD1-GXXDownload RCD 4800 Product BriefServer RDIMM

How the DDR5 Registering Clock Driver Works

The Rambus DDR5 RCD provides Command/Address (CA) and clocks to the DDR5 memory devices in RDIMMs. In DDR5 DIMM architectures, the module is organized into two independent 40-bit subchannels (32 bits data, 8 bits ECC). Each subchannel is organized as either 10 devices in a x4 configuration with 2 ranks or 5 devices in a x8 configuration with 2 ranks. The RCD distributes C/A signals and clocks for each subchannel, rank and nibble. Sideband channel communication with the CPU or motherboard Baseboard Management Controller (BMC) is enabled through a 12.5 MHz (max.) I3C bus interface.  

Features of the DDR5 RCD 

  • Supports data rates up to 9600 MT/s 
  • Supports clock rates up to 4800 MHz 
  • Supports double data rate (DDR) and single data rate (SDR) CA bus 
  • Supports two independent subchannels per RDIMM 
  • Supports two physical ranks per subchannel, four physical ranks total 
  • Supports up to 16 logical ranks (per physical rank) for high capacity RDIMMs 
  • Low Power 1.1V VDD 
  • 12.5 MHz (max.) I3C bus interface 
DDR5 RCD High-Level Functional Block Diagram
DDR5 RCD High-Level Functional Block Diagram

Data Center Evolution: DDR5 DIMMs Advance Server Performance

Data Center Evolution: DDR5 DIMMs Advance Server Performance cover

Agentic AI is reshaping data center architectures, introducing persistent, memory-intensive workloads that demand unprecedented bandwidth, capacity, and efficiency from system memory. Unlike traditional AI/ML pipelines, agentic systems operate in continuous, context-rich loops that amplify the importance of main memory as a critical performance enabler. This white paper explores how DDR5 DIMMs address these emerging requirements, delivering significant advancements in data rate, density, power efficiency, and channel architecture over DDR4. It examines the role of DDR5 as the foundational memory layer in modern AI infrastructure, complementing heterogeneous compute architectures and supporting highly concurrent, data-driven workloads, while also outlining the key design considerations required to achieve reliable, high-performance operation in next-generation servers.

Rambus logo