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DDR5 Server Power Management ICs (DDR5 PMICs)
The Rambus DDR5 PMICs enable a broad range of server Registered DIMM (RDIMM) performance and capacity configurations. The PMIC5030 will be used in all RDIMM 8000 designs. In addition, the PMIC5020 supports MRDIMM 8800, and the PMIC5030 will be used in MRDIMM 12800 (and above) modules.
| Description | Part Number | Product Brief | Applications |
|---|---|---|---|
| PMIC5000 High Current Power Management IC | P1945XXGxx |  | Server RDIMM 4800 – 7200 |
| PMIC5020 Extreme Current Power Management IC | P1947XXGxx | | 4800 – 7200, MRDIMM 8800 |
| PMIC5030 Gen2 Server Power Management IC | P2965XXGxx | | RDIMM 8000, MRDIMM 12800 |
How the DDR5 Server PMICs Work
In order to deliver higher levels of performance at high reliability and within the desired power envelope, DDR5 implements a number of memory module architecture changes vs. previous generation DDR4. One of these changes is to move the power management ICs from the motherboard to the individual DDR5 memory modules.
The DDR5 on-module PMIC receives a 12V input and generates the distinct voltage levels needed by the various components on the DDR5 module. This saves motherboard real estate and eliminates the need for motherboard voltage regulators that must be designed for the fully-populated memory module use case.
With PMICs on the DDR5 DIMMs, power management is added on an incremental basis that scales with the number of memory modules needed by the system configuration. Another advantage of this power architecture is that it greatly reduces the problem of IR drop on the delivery network by delivering the high voltage 12V supply to the module, as opposed to trying to deliver 1V from the motherboard, through the module connector and onto the memory module. This provides tighter voltage tolerances for the sensitive components on the DIMM, which helps achieve the higher DDR5 performance level targets.
Ask the Experts: DDR5 Memory Interface Chips with John Eble
In this episode of Ask the Experts, we sat down with Rambus memory expert John Eble to learn what’s new with DDR5 server memory modules (RDIMMs). Join us as we chat about the chips in DDR5 memory’s new RDIMM architecture, the importance of memory module PMICs, new Rambus DDR5 server PMIC products, and timing and enablement of DDR5 7200 server platforms.
Features of DDR5 Server PMICs (PMIC5000, PMIC5020)
- I2C and I3C Basic bus serial interface support
- Meets or exceeds all JESD300-5 performance specifications up to 1MHz for I2C and 12.5MHz for I3C Basic bus serial interface
- Parity error check and packet error check (PEC) function
- In-band Interrupt (IBI) support
- VIN_Bulk input operational at 4.25V to 15V
- VIN_Mgmt input operational at 3V to 3.6V
- Four step-down switching regulators (SWA, SWB, SWC, and SWD) and 3 LDO regulators (VBias, VOUT_1.8V, VOUT_1.0V)
- Write protect and programmable modes of operation
- I2C bus operational at 1.0V to 3.3V nominal I/O levels
- I3C Basic bus operational at 1.0V, 1.1V, and 1.2V nominal I/O levels
- Dynamic driver switching capability for I3C Basic bus operation between push-pull and open-drain
- Operation from -100°C to +125°C
- 35-pin thermally enhanced FCQFN package
Data Center Evolution: DDR5 DIMMs Advance Server Performance
Agentic AI is reshaping data center architectures, introducing persistent, memory-intensive workloads that demand unprecedented bandwidth, capacity, and efficiency from system memory. Unlike traditional AI/ML pipelines, agentic systems operate in continuous, context-rich loops that amplify the importance of main memory as a critical performance enabler. This white paper explores how DDR5 DIMMs address these emerging requirements, delivering significant advancements in data rate, density, power efficiency, and channel architecture over DDR4. It examines the role of DDR5 as the foundational memory layer in modern AI infrastructure, complementing heterogeneous compute architectures and supporting highly concurrent, data-driven workloads, while also outlining the key design considerations required to achieve reliable, high-performance operation in next-generation servers.
