At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
DDR5 Temperature Sensor Chip
The Rambus DDR5 Temperature Sensor (TS1685XGxx) enables DDR5 Registered DIMMs (RDIMMs) for servers, workstations and storage systems.
| Description | Part Number | Product Brief | Applications | Status |
|---|---|---|---|---|
| Temperature Sensor | TS1685XGxx |  | Server RDIMM | In Production |
How the DDR5 Temperature Sensor Works
The DDR5 Temperature Sensor device incorporates thermal sensing capability which is controlled and read over I2C and I3C Basic bus serial interface. The TS5 device operates from 1.8V nominal power supply input. The TS5 device is intended to operate up to 12.5 MHz on a 1.0V to 1.2V I3C Basic bus or up to 1 MHz on a 1.0V to 1.2V I2C bus.
The TS5 device is intended to interface to I2C/I3C Basic buses which have multiple devices on a shared bus and must be uniquely addressed with fixed addressing on the same bus. The TS5 device responds to specific pre-defined I2C/I3C Basic device select codes on the serial interface bus.
Features of the DDR5 Temperature Sensor
- I2C and I3C Basic bus serial interface support
- Meets or exceeds all JESD302-1 performance specifications up to 1MHz for I2C and 12.5MHz for I3C Basic bus serial interface
- Thermal sensing capability
- 6-ball WLCSP package, MO-229 var V/W/ECED-3; 0.8 mm x 1.3 mm
- Parity error check and packet error check (PEC) function
- In-band Interrupt (IBI) support
- Operational at 1.8V +10%/- 5%
- I2C and I3C Basic bus operational at 1.0V, 1.1V, and 1.2V nominal I/O levels
- Dynamic driver switching capability for I3C Basic bus operation between push-pull and open-drain
- Meets or exceeds all JEDEC Temperature Sensor Device operational requirements
- Precision thermal sensing
- I2C and I3C bus serial interface support
- Low latency for fastest I3C bus rates
- Meets or exceeds all JEDEC DDR5 Temperature Sensor operational requirements (JESD302-1.01)
Data Center Evolution: DDR5 DIMMs Advance Server Performance
Agentic AI is reshaping data center architectures, introducing persistent, memory-intensive workloads that demand unprecedented bandwidth, capacity, and efficiency from system memory. Unlike traditional AI/ML pipelines, agentic systems operate in continuous, context-rich loops that amplify the importance of main memory as a critical performance enabler. This white paper explores how DDR5 DIMMs address these emerging requirements, delivering significant advancements in data rate, density, power efficiency, and channel architecture over DDR4. It examines the role of DDR5 as the foundational memory layer in modern AI infrastructure, complementing heterogeneous compute architectures and supporting highly concurrent, data-driven workloads, while also outlining the key design considerations required to achieve reliable, high-performance operation in next-generation servers.
