Bart Stevens, Senior Director of Product Marketing for Security IP, discusses the security challenges of AI inference processing in both cloud-based data centers and edge devices. He emphasizes the need for robust security measures to protect valuable AI models and sensitive data across various deployment environments. He covers essential cryptographic principles, confidential computing, and key security mechanisms such as data at rest, in use, and in motion protection. Bart highlights the differences in security requirements between data centers and edge devices due to operational constraints and threat models.
Creating a Secure Infrastructure for Advanced AI Workloads
Security Challenges in a World of AI Everywhere
Scott Best, Senior Director of Anti-Tamper Technology at Rambus, discusses the security challenges associated with AI chips and their growing deployment at the edge. Best highlights the similarities between AI chips and FPGAs, particularly in their vulnerability to attacks on valuable firmware assets, such as neural net models and RTL. He explores the importance of securing firmware from tampering and theft, emphasizing the need for encryption and authenticity verification. Best also delves into the rising threats posed by side-channel attacks like Differential Power Analysis (DPA) and offers novel solutions such as key hash chaining to protect firmware while maintaining boot efficiency. He concludes by discussing emerging risks, including neural net model extraction, and suggests tailored countermeasures to safeguard AI architectures from these attacks.
From Training to Inference: HBM, GDDR & LPDDR Memory
Nidish Kamath, director of product management for Rambus Memory Controller IP, discusses the company’s HBM, GDDR, and LPDDR solutions that address AI training and inference workload requirements. Nidish explains the differences between AI training and inference, highlighting the unique compute and memory needs of each. He will delve into the architectural innovations of HBM, including its 2.5D and 3D memory architecture, and the evolution of HBM memory to meet AI demands. Additionally, Nidish will cover advancements in GDDR and LPDDR memory technologies, emphasizing their roles in AI inference and mobile devices.
Navigating the Dynamics of IP Licensing for Data Center & AI
Raj Uppala, Senior Director of Marketing and Partnerships at Rambus, explores the complexities of IP licensing for emerging data center and AI applications. He discusses the growing demand for specialized IP components such as memory controllers, security solutions, and high-performance interfaces driven by the rise of AI accelerators and SoCs. Raj highlights the key factors customers consider when evaluating IP solutions, such as time-to-market, scalability, interoperability, and cost-effectiveness. The presentation underscores the importance of choosing the right IP solutions to accelerate innovation and streamline development in high-performance computing and AI infrastructure.
Why PCIe and CXL are Critical Interconnects for the AI Era
Lou Ternullo, Senior Director of IP Product Management at Rambus, discusses the critical role of PCIe and CXL interconnects in enabling the AI-driven data centers of tomorrow. He explores the challenges of traditional server setups, such as inefficiencies in resource allocation, over-provisioning, and data replication, and presents disaggregation as a solution to improve cost-efficiency and performance. By leveraging PCIe and CXL interconnects, data centers can enable heterogeneous compute, memory sharing, and lower-latency communication across servers and racks. Lou underscores the importance of these interconnect technologies in reducing latency, optimizing resource use, and lowering costs in AI-focused data centers.
The Road Ahead for Main Memory in the Data Center
Carlos Weissenberg, Product Marketing Manager for Memory Interface Chips at Rambus, discusses the increasing demands for memory driven by AI and high-performance computing. Carlos will explain the innovations incorporated in DDR5 memory modules, such as the dual-channel architecture and improved power management, designed to meet the growing memory requirements of data center servers. He will also discuss how the DDR5 memory interface chipset enables higher performance and greater capacity required by advanced server workloads.
