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At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.

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HBM4 Memory: Break Through to Greater Bandwidth

HBM4 Memory: Break Through to Greater Bandwidth

AI/ML’s demands for greater bandwidth are insatiable driving rapid improvements in every aspect of computing hardware and software. HBM memory is the ideal solution for the high bandwidth requirements of AI/ML training, but it entails additional design considerations given its 2.5D architecture. Now we’re on the verge of a new generation of HBM that will raise memory and capacity to new heights. Designers can realize new levels of performance with the HBM4-ready memory subsystem solution from Rambus.

Network Security at Terabit-per-second Rates with MACsec, IPsec and UEC

[Live on September 17 @ 9am PT] Join Maxim Demchenko as he discusses the use of MACsec and IPsec as today’s security protocols, and how the next generation of AI/HPC systems are moving towards Ultra Ethernet with its own Layer 3 network security called TSS. We’ll also cover the scaling of Ethernet rates to 1.6 Tbps and beyond. Plus, you will learn about the Rambus high-speed network security IP portfolio including the latest Rambus MACsec IP supporting full 1.6 Tbps Ethernet. Join us to learn how to build a solution that meets the performance and security demands of current and future systems.

MACsec Fundamentals

For end-to-end security of data and devices, data must be secured both when it as rest (stored on a connected device) and when it is in motion (communicated between connected devices). For data at rest, a hardware root of trust anchored in silicon provides that foundation upon which all device security is built. Similarly, MACsec security anchored in hardware at the foundational communication layer provides that basis of trust for data in motion.

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