The Rambus Compute Express Link (CXL) 3.1 Controller with AXI leverages a silicon-proven PCIe controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. Download the brief to see the features and the specs.
CXL 3.1 Controller with AXI Product Brief
CXL 3.1 Controller Product Brief
The Rambus Compute Express Link (CXL) 3.1 Controller leverages a silicon-proven PCIe controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. Download the brief to learn the features and the specs.
Compute Express Link (CXL): All you need to know
In this blog post, we take an in-depth look at Compute Express Link®™ (CXL®™), an open standard cache-coherent interconnect between processors and accelerators, smart NICs, and memory devices.
- We explore how CXL can help data centers more efficiently handle the tremendous memory performance demands of generative AI and other advanced workloads.
- We discuss how CXL technology maintains memory coherency between the CPU memory space and memory on attached devices to enable resource sharing (or pooling).
- We also detail how CXL builds upon the physical and electrical interfaces of PCI Express® (PCIe®) with protocols that establish coherency, simplify the software stack, and maintain compatibility with existing standards.
- Lastly, we review Rambus CXL solutions, which include the Rambus CXL 3.1 Controller. This IP comes with integrated Integrity and Data Encryption (IDE) modules to monitor and protect against cyber and physical attacks on CXL and PCIe links.
PCIe 6.1 – All you need to know
The PCI Express® 6.0 (PCIe® 6.0) specification was released by PCI-SIG® in January 2022. This new generation of the ubiquitous PCIe standard brought with it many exciting new features designed to boost performance for compute-intensive workloads including data center, AI/ML and HPC applications. PCIe 6.0 has now evolved to version 6.1 of the standard. Find out all about PCIe 6.1 in the article below.
Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.1
The PCI Express® (PCIe®) interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the torrid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.1 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard.
PCIe 6.1 Controller Product Brief
The Rambus PCIe 6.1 Controller is configurable and scalable controller IP designed for ASIC implementation. Download the brief to learn about the features and the specs.