Vehicle systems and the semiconductors used within them are some of the most complex electronics seen today. In the past, electronics going into vehicle systems implemented flat architectures with isolated functions controlling various components of the power train and vehicle dynamics. However, to support the realization of Level 4 and Level 5 (L4/L5) autonomous driving, a massive restructure is underway. The software-defined vehicle, the automotive Ethernet, vehicle-to-everything (V2X) connectivity, and domain controller units are just some of the new technologies required to realize L4/L5 capabilities. Ensuring all these new systems are both functionally safe and secure from cyberattacks is mission critical.
The growth of computing, graphics, neural processing power, communication bandwidth, and storage capacities have enabled amazing solutions. These innovations have created great value for society, and that value must be protected from exploitation by adversaries. This whitepaper explores many of these major technology changes and how Rambus’ security offerings help in tackling the new embedded security challenges of device and silicon manufacturers.
The PCI Express® (PCIe®) interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the torrid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.0 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard.
In this 451 Research analysis, the report describes Compute Express Link Consortium’s acquisition of Gen-Z Consortium, seeking “to establish cache-coherent interconnects for processors, memory expansion and accelerators.” Read how this consolidation could positively affect both memory semantic protocols that enable high-speed connectivity to processors, accelerators and memory expansion technologies and the overall market.
PUFs are mixed-signal circuits which rely on variations unique to a specific chip to self-generate a digital “fingerprint.” Most PUFs require a “helper-data” image that is generated during the initial digitization process, also known as Enrollment. Leveraging the chip-unique transformation function of PUFs and encrypted helper data, an unclonable challenge-response mechanism can be implemented that can distinguish authentic chips from perfect adversarial clones.
AI/ML’s demands for greater bandwidth are insatiable driving rapid improvements in every aspect of computing hardware and software. HBM memory is the ideal solution for the high bandwidth requirements of AI/ML training, but it entails additional design considerations given its 2.5D architecture. Now we’re on the verge of a new generation of HBM that will raise memory and capacity to new heights. Designers can realize new levels of performance with the HBM3-ready memory subsystem solution from Rambus.