For over 30 years, DRAM has continuously adapted to the needs of each new wave of hardware spanning PCs, game consoles, mobile phones and cloud servers. Each generation of hardware required DRAM to hit new benchmarks in bandwidth, latency, power or capacity. Looking ahead, the 2020s will be the decade of artificial intelligence/machine learning (AI/ML) touching every industry and application space. For DRAM, AI/ML represents the biggest challenge yet with a list of requirements for “all of the above.”
Part of a full suite of memory controller add-on cores, the In-Line Error Correction Coding (In-Line ECC) core works with the Northwest Logic GDDR6 and LPDDR4 Controller cores. The In-Line ECC implements the standard Hamming Code-based DRAM Single Error Correction (SEC) and Double Error Detection (DED) algorithm.
The Rambus PCI Express® (PCIe) 5.0 interface is optimized for power and efficiency delivering maximum performance for applications in AI, 5G, Edge, Data Center and Graphics. The interface is a low-power, area-optimized, silicon IP designed with a system-oriented approach to maximize flexibility and ease of integration. It consists of a co-verified PHY and digital controller providing a complete PCIe 5.0 SerDes subsystem.
Artificial Intelligence/Machine Learning (AI/ML) growth proceeds at a lightning pace. In the past eight years, AI training capabilities have jumped by a factor of 300,000 driving rapid improvements in every aspect of computing hardware and software. Meanwhile, AI inference is being deployed across the network edge and in a broad spectrum of IoT devices including in automotive/ADAS. Training and inference have unique feature requirements that can be served by tailored memory solutions. Learn how HBM2E and GDDR6 provide the high performance demanded by the next wave of AI applications.
This IDC Technology Spotlight, sponsored by Rambus, highlights the fifth generation of cellular network technology (5G) is scaling further in 2020, enabling a new wave of AI-powered end points. To remain competitive, manufacturers must implement enhanced security measures on edge and IoT devices designed for the increased performance in speed, latency, and connection density.
The Rambus HBM2E interface is fully compliant with the JEDEC JESD235B standard. It supports data rates up to 3.2 Gbps per data pin. The interface features 8 independent channels, each containing 128 bits for a total data width of 1024 bits. The resulting bandwidth is 410 GB/s per stack, with the stack consisting of 2, 4, 8 or 12 DRAMs. Consisting of a co-verified PHY and controller, it comprises a complete HBM2E memory interface subsystem.