Papers

Part of a full suite of memory controller add-on cores, the Error Correction Coding (ECC) core implements the standard Hamming Code-based DRAM Single Error Correction (SEC) and Double Error Detection (DED) algorithms. The Read-Modify-Write core, offered separately, can be used in conjunction with the ECC Core when dealing with misaligned bursts.

The Northwest Logic Expresso 4.0 Digital Controller is designed to achieve maximum PCI Express (PCIe) 4.0 performance with great design flexibility and ease of integration. It comprises a complete SerDes subsystems with the Rambus PCIe 4.0 PHY or can integrate with PIPE 4.2-compliant 3rd-party PHYs. The Expresso 4.0 controller supports PCIe 4.0, 3.0, 2.1 and 1.1.

Part of a full suite of PCI Express (PCIe) controller add-on cores and drivers, the Expresso DMA Bridge Core provides high-performance DMA and/or bridging between PCIe and AXI for both Endpoint and Root Port applications.

Part of a full suite of PCI Express (PCIe) controller add-on cores and drivers, the Expresso Testbench emulates a Root Complex device enabling simulation of a PCI Express design.

Part of a full suite of PCI Express (PCIe) controller add-on cores and drivers, the Expresso DMA Driver is specifically designed to be used with the Expresso DMA Bridge core. It supports all DMA modes supported by the Expresso DMA Bridge core. Together they provide a complete, pre-packaged, flexible DMA solution.

Part of a full suite of PCI Express (PCIe) controller add-on cores and drivers, the AXI DMA Back-End Core provides high-performance, scatter gather DMA operation in a flexible fashion. It can be easily integrated and used in a wide variety of DMA-based systems.