In this 451 Research analysis, the report describes Compute Express Link Consortium’s acquisition of Gen-Z Consortium, seeking “to establish cache-coherent interconnects for processors, memory expansion and accelerators.” Read how this consolidation could positively affect both memory semantic protocols that enable high-speed connectivity to processors, accelerators and memory expansion technologies and the overall market.
Papers
Anti-Tamper Benefits of Encrypted Helper-Data Images for PUFs
PUFs are mixed-signal circuits which rely on variations unique to a specific chip to self-generate a digital “fingerprint.” Most PUFs require a “helper-data” image that is generated during the initial digitization process, also known as Enrollment. Leveraging the chip-unique transformation function of PUFs and encrypted helper data, an unclonable challenge-response mechanism can be implemented that can distinguish authentic chips from perfect adversarial clones.
CXL Memory Interconnect Initiative: Enabling a New Era of Data Center Architecture
In response to an exponential growth in data, the industry is on the threshold of a groundbreaking architectural shift that will fundamentally change the performance, efficiency and cost of data centers around the globe. Server architecture, which has remained largely unchanged for decades, is taking a revolutionary step forward to address the growing demand for data and the voracious performance requirements of advanced workloads.
Security Solutions for AI/ML
AI/ML is increasingly pervasive across all industries driven by a massive wave of digitization. Data, the raw material of AI/ML and Deep Learning algorithms, is available in enormous quantities from all aspects of business operations. AI/ML promises great gains in responsiveness and adaptability in an ever-changing technology landscape, and industries are enthusiastically responding to that appeal. Concurrently, the vast value creation of AI/ML make it an inviting target for adversaries who aim to compromise or steal. Learn about the attack vectors against AI/ML and solutions for safeguarding its assets.
Data Center Evolution: Accelerating Computing with PCI Express 5.0
The PCI Express® (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), require the new level of performance of PCI Express 5.0.
Security in the ARM Ecosystem
Building security in an SoC aiming to meet the goals set by the ARM Platform Security Architecture (PSA) is a complex matter. This is compounded by the complexity of modern-day SoCs comprising multiple processors, security domains and security levels. The Rambus root of trust provides a solid foundation for the SoC security architecture ticking ‘all the boxes’ for reaching the security goals, while offering extensive support for effective integration into a complex TrustZone-based SoC infrastructure.
