The virtuous cycle of increased computing power enabling new applications which demand more computing power continues unabated. Today, applications spanning AI, autonomous vehicles, video streaming, AR and VR all demand more bandwidth, lower latencies and higher speeds. In response, the SoCs powering the terabit routers and switches at the heart of the network must run even faster. The upgrade to 112G SerDes represents the latest advancement in high-speed signaling technology enabling communication within and between network devices.
Memory + Interfaces
The Rambus 112G LR MPS PHY is a comprehensive IP solution designed to provide reliable performance across challenging long-reach signaling environments for next-generation networks and hyper-scale data centers. It supports PAM-4 and NRZ signaling and data rates from 10.31 to 106.25 Gbps across copper and backplane channels with more than 35dB insertion loss. At the heart of the 112G MPS architecture is an ADC operating at 56 GS/s that allows for adjustable power and improved performance while providing low BER.
With GDDR PHYs providing a maximum bandwidth of up to 64 GB/s, it is critical for ASIC designers to ensure that devices and systems aren’t affected by signal integrity issues. This is precisely why the Rambus GDDR6 PHY engineering team makes extensive use of modeling and simulation tools, as well as providing highly-programmable circuits, debug interfaces and utilities. Moreover, our engineering team comprises a range of in-house experts that participate in all stages of the GDDR6 PHY design which is available on leading FinFET process nodes. These include package and PCB design experts and layout gurus, as well as signal integrity and power integrity specialists. On the engineering side, the Rambus GDDR6 PHY leverages our system-aware design methodology to facilitate flexible product integration. Specifically, we provide full system signal and power integrity analysis to optimize performance and chip layout.
The Rambus GDDR6 (Graphics Double Data Rate) Memory PHY is designed for the communication to and from high-speed, high-bandwidth GDDR6 SGRAM (Synchronous Graphics Random Access) memory. Originally designed for graphics applications, it is a high-performance memory solution that can be used in a variety of high-performance applications that require large amounts of data computation like artificial intelligence (AI), crypto mining, deep learning, autonomous vehicles, and high-speed networking.
GDDR6 offers higher densities compared to previous-generation graphics memory. In addition, GDDR6 doubles the speed (12–16 Gb/s) of GDDR5 and provides more than 5X the 3.2 Gb/s speed of DDR4. Moreover, GDDR6 supports the same low external voltage (1.35V) as GDDR5X, although it is based on a dual-channel architecture instead of GDDR5X’s single-channel architecture. With initial shipments beginning in 2018, GDDR6 will be deployed across multiple verticals, including the graphics market, the data center/networking space and automotive sector.
The Rambus NVRCD is the industry’s 1st JEDEC-standard persistent memory register clock driver (NVRCD) in full production for use with NVDIMM-N and emerging NVDIMM-P solutions. This chipset is our complete application-specific standard product (ASSP) solution that is reliable and cost effective. This NVRCD enables persistent memory R-DIMMs and LR-DIMMs operating at speeds up to DDR4-3200.