With GDDR PHYs providing a maximum bandwidth of up to 64 GB/s, it is critical for ASIC designers to ensure that devices and systems aren’t affected by signal integrity issues. This is precisely why the Rambus GDDR6 PHY engineering team makes extensive use of modeling and simulation tools, as well as providing highly-programmable circuits, debug interfaces and utilities. Moreover, our engineering team comprises a range of in-house experts that participate in all stages of the GDDR6 PHY design which is available on leading FinFET process nodes. These include package and PCB design experts and layout gurus, as well as signal integrity and power integrity specialists. On the engineering side, the Rambus GDDR6 PHY leverages our system-aware design methodology to facilitate flexible product integration. Specifically, we provide full system signal and power integrity analysis to optimize performance and chip layout.
Memory + Interfaces
The Rambus GDDR6 (Graphics Double Data Rate) Memory PHY is designed for the communication to and from high-speed, high-bandwidth GDDR6 SGRAM (Synchronous Graphics Random Access) memory. Originally designed for graphics applications, it is a high-performance memory solution that can be used in a variety of high-performance applications that require large amounts of data computation like artificial intelligence (AI), crypto mining, deep learning, autonomous vehicles, and high-speed networking.
GDDR6 offers higher densities compared to previous-generation graphics memory. In addition, GDDR6 doubles the speed (12–16 Gb/s) of GDDR5 and provides more than 5X the 3.2 Gb/s speed of DDR4. Moreover, GDDR6 supports the same low external voltage (1.35V) as GDDR5X, although it is based on a dual-channel architecture instead of GDDR5X’s single-channel architecture. With initial shipments beginning in 2018, GDDR6 will be deployed across multiple verticals, including the graphics market, the data center/networking space and automotive sector.
The Rambus NVRCD is the industry’s 1st JEDEC-standard persistent memory register clock driver (NVRCD) in full production for use with NVDIMM-N and emerging NVDIMM-P solutions. This chipset is our complete application-specific standard product (ASSP) solution that is reliable and cost effective. This NVRCD enables persistent memory R-DIMMs and LR-DIMMs operating at speeds up to DDR4-3200.
The Rambus PCI Express (PCIe) 4.0 SerDes PHY is designed to maximize interface speed in the difficult system environments found in high-performance computing. It is a low-power, area-optimized, silicon-proven IP designed with a system-oriented approach to maximize flexibility and ease integration for our customers. The PCIe 4 SerDes PHY supports PCIe 4.0, 3.0, and 2.0 and has full support for manufacturability.
This paper will discuss the various challenges of designing high speed SerDes, as well as the importance of detailed modeling and design of highly programmable circuits and debug interfaces.