Fully compliant with LPDDR3 and LPDDR2 DRAM specifications, our LPDDR3 PHY pairs with the LPDDR3 DRAM to create a memory subsystem that supports data rates of up to 2133 Mbps, and reduces active memory system power by up to 25% and active DRAM power by up to 30%. This enables a significantly improved thermal profile and an increased battery life in the end device. The improved thermal profile also enables the memory system to run at peak bandwidth for longer periods of time, which translates to better overall performance in the end systems.
The improvement in power consumption is a result of Low Voltage Swing Terminated Logic (LVSTL), a single-ended, ground-terminated signaling technology, used while in R+ mode. LVSTL features a significantly reduced signal swing versus the 1.2 volt HSUL (High Speed Unterminated Logic) signal swing of standard LPDDR3. Reduced signal swing translates to significantly reduced IO power at high data rate, which is a major component of DRAM power. By supporting LVSTL and HSUL signaling, LPDDR3 offers a low-power mode while maintaining compatibility with LPDDR3 and LPDDR2 DRAM standards.
