Ed Sperling of Semiconductor Engineering recently noted that adding more cores to a processor doesn’t necessarily improve system performance. In fact, designing the wrong size or type of core may actually waste power. “This has set the stage for a couple of broad shifts in the semiconductor industry,” Sperling explained. “Memory architectures can play an important role here. Most of the current approaches use on-chip SRAM and off-chip DRAM. But different packaging options, coupled with different memory architectures, can change the formula.”
Smart Data Acceleration
Going beyond DRAM with Smart Data Acceleration
Ed Sperling of Semiconductor Engineering recently noted that new memory types and approaches are being developed as Moore’s Law begins to slow. “What fits where in the memory hierarchy is becoming less clear as the semiconductor industry grapples with these changes,” he explained. “New architectures, such as fan-outs and 2.5D, raise questions about how many levels of cache need to be on-die, and whether high-speed connections and shorter distances can provide equal or better performance off-chip.”
A closer look at Rambus’ SDA research platform
Rambus’ Smart Data Acceleration (SDA) research platform focuses on architectures designed to offload computing closer to very large data sets at multiple points in the memory and storage hierarchy. Potential use case scenarios include real-time risk analytics, ad serving, neural imaging, transcoding and genome mapping.
Rambus partners with Los Alamos National Laboratory on smart data acceleration
The Los Alamos National Laboratory (LANL) is currently evaluating various aspects of Rambus’ Smart Data Acceleration (SDA) Research Program. Deployed at LANL, the SDA platform is designed to optimize the performance of in-memory databases, graph analytics and other Big Data applications.
A modular approach to Big Data
Driven by Big Data and new applications, modern servers and data centers are out of synch with current demands – due to increasing requirements for real-time access to large amounts of information. That is precisely why Rambus’ Smart Data Acceleration (SDA) research program focuses on architectures designed to offload computing closer to very large data sets at multiple points in the memory and storage hierarchy.