As artificial intelligence transforms industries and redefines computing, memory technologies are foundational to fueling the performance, scalability, and efficiency of AI systems. RDS 2025 explores how memory innovation is enabling the AI revolution from data centers to client devices.
Rambus Design Summit 2025 (RDS 2025), tailored for system and chip design engineers, explores the critical role of memory in enabling artificial intelligence. From the evolution of memory over the past 35 years to cutting-edge solutions for servers, accelerators, and client systems, this virtual conference showcases how Rambus technologies are driving AI performance at every level.
Attendees will gain insights into Rambus memory chip solutions for data center and client platforms, memory IP for high-performance AI accelerators, and interconnect IP technologies to scale AI infrastructure. A roundtable with Rambus experts will provide perspectives on trends and future directions in memory innovation.
Time | Session | Featured Speakers |
---|---|---|
8:00 AM – 8:45 AM | 35 Years of Memory Innovation for AI | Steven Woo |
8:45 AM – 9:30AM | Memory Interface Chip Solutions for Servers and AI in the Data Center | Zaman Mollah |
9:30 AM – 10:15 AM | Memory Interface Chip Solutions for PC Clients and AI | Carlos Weissenberg |
10:15 AM – 11:00 AM | How AI is Shaping the Memory Market | Dr. Steve Woo, John Eble, Nidish Kamath, Tim Messegee |
11:00 AM – 11:45 AM | Memory IP for AI Accelerators: HBM4, LPDDR5, and GDDR7 | Nidish Kamath |
11:45 AM – 12:15 PM | Scaling AI Infrastructure with PCIe 7 and CXL 3 | Lou Ternullo |
Time | Session | ||||||
---|---|---|---|---|---|---|---|
8:00 AM – 9:00 AM |
35 Years of Memory Innovation for AI
|
||||||
9:00 AM – 10:00AM |
Memory Interface Chip Solutions for Servers and AI in the Data Center
|
||||||
10:00 AM – 11:00 AM |
Memory Interface Chip Solutions for PC Clients and AI
|
||||||
11:00 AM – 12:00 PM |
How AI is Shaping the Memory Market
|
||||||
12:00 PM – 1:00 PM |
Memory IP for AI Accelerators: HBM4, LPDDR5, and GDDR7
|
||||||
1:00 PM |
Why PCIe & CXL are Critical Interconnects for the AI Era
|