October 8, 2020
Join us for a day of virtual sessions covering the selection and implementation of IP solutions for the data center, 5G/edge and IoT devices including advancing the performance of AI/ML applications.
Connect with a community of industry experts and gain insights and practical information for the implementation of their next-generation SoCs. Register to secure your spot here.
John C. Eble received his B.Cmp.E. (’93), M.S.E.E (’94), and Ph.D. EE (’99) from Georgia Tech. From 1998 to 2001 he worked at Compaq on EV7 high-speed I/O circuits in the Alpha Microprocessor Development Group. He then joined Velio Communications as a circuit designer. In 2003, he joined Rambus Inc. where he has held many engineering and research management roles and specialized in the design of high-speed I/O and next-generation memory interconnect architectures. He has authored over 30 technical publications, 10 patents, and a book chapter. He is currently VP of Product Marketing for Rambus’ memory interconnect chip business unit.
VP, Product Marketing, Rambus
Sr. Director, Product Marketing, Rambus
Joe Gow is the Senior Director of the Secure Provisioning and Cloud Security Services businesses for Rambus Security. In this role, Joe is responsible for defining and delivering innovative security solutions that address the factory provisioning needs of semiconductor and OEM companies that enable chips and devices to be trusted throughout their lifetime, helping to ensure the integrity of the semiconductor supply chain. These manufacturing security solutions are supported by cloud-based key and certificate management services that enable OEMs and managed service providers (MSPs) to leverage this trust to manage the identity and security of connected things. Prior to Rambus, Joe has held product and business management leadership roles with leading enterprise security software and cloud security companies including Symantec, GuardienEdge, Avaya, Websense, and Elemental Security.
Sr. Director, Product Management, Rambus
Matt Jones is the General Manager for the IP Cores Business Unit at Rambus. He is responsible for development and growth of the company’s interface IP products, driving memory and interconnect architectural innovation in Data Center and Edge Connectivity applications. Before joining Rambus, Matt held various product line management and marketing positions for microprocessor, connectivity and power management products over a twenty-four-year career at IDT, later acquired by Renesas. Matt holds a Bachelor of Science in Electrical Engineering and a Bachelor of Arts in Economics from Stanford University.
Sr. Director and GM, Rambus IP Cores
Phani Paladugu is Director of Field Application Engineering at Rambus, responsible for interface and memory IP cores. Before joining Rambus, Phani was a Senior Manager, Interface IP applications at Cadence. Prior to this role, he spent more than 10 years at Aricent, ST Microelectronics and has extensive experience in designing high speed interfaces for ethernet, storage, networking and automotive applications. Phani holds a MS in Electrical Engineering from National Institute of Technology, Warangal, India.
Director, Field Applications Engineering, Rambus
Neeraj is currently the VP and GM at Rambus Security BU, based out of Silicon Valley, CA. He has 20+ years of semiconductors engineering experience in compute and security domains. At Rambus, Neeraj is responsible for the CryptoManager Secure Silicon IP and Provisioning products. Before joining Rambus, Neeraj founded Kryptos Solutions, where he built an ultra-secure endpoint platform for high-risk government applications. Prior to that, Neeraj was the VP of Engineering at NXP Semiconductors, responsible for major OEM design-win for NXP’s NFC based secure payment platform. Neeraj also held various engineering positions at IBM and Intel working on gaming processors, and CPU products.
Neeraj graduated with a Master of Technology degree in Solid State Materials from the Indian Institute of Technology in Delhi, India. He attended the Stanford Executive Program at Stanford University, California.
Shane Rau leads IDC's computing semiconductor research within IDC's Enabling Technologies team. Mr. Rau's research covers microprocessors and SoCs, discrete graphics processors (GPUs), FPGAs, and artificial intelligence (AI) accelerators in systems across the internet, including in the data center, in PCs, and at the edge, such as embedded and intelligent systems.
Mr. Rau provides in-depth insight and intelligence on market sizing, forecasting, technology trends, vendors, pricing trends, and market share. Through collaboration with PC, server and embedded systems analysts colleagues, Mr. Rau spearheads IDC research initiatives into system supply chains, technologies and interface attach rates, as well as into the changing semiconductor vendor market power dynamics.
Research Vice President, Computing Semiconductors, IDC
Joe Rodriguez is a Product Marketing Manager with the Rambus Controller Group. He is an expert at Memory IP and MIPI controller IP for Enterprise, Cloud, Networking, IoT, AI and Mobile applications. Before joining Rambus, Joe held Product and Technical Marketing Management positions at the Mentor Graphics Design Verification Division. Prior to that, he was an expert in emulation as a Field Engineer for Cadence Design Systems and a Modeling Engineer at Synopsys.
Product Marketing Manager, Rambus
Ed Sperling is the editor in chief of Semiconductor Engineering. He is a technology industry veteran and frequent moderator and speaker in Silicon Valley. Sperling is a former contributing editor at Forbes, and former editor in chief of Electronic News and Electronic Business. Prior to that he held top editorial positions at Ziff-Davis and CMP Publications.
Editor in Chief, Semiconductor Engineering
Sr. Director of Product Management, Rambus
Fellow and Distinguished Inventor
9:00am – 10:45am PST – Protecting Data at Rest and in Motion
With the rising value of data travelling across the global network, implementing robust hardware-level security is more important than ever. Technology experts from the Rambus security business will discuss the methodology of security by design, and the implementation of hardware root of trust and protocol engine solutions. A live Q&A session will follow the presentations.
11:00am – 11:45am PST – Roundtable: Data Center Evolution
IDC research vice president, Shane Rau, will lay out the macro trends that are shaping the future of the data center, and the impact on compute and network device architectures. Technology leaders from across Rambus will share the chip and IP solutions that can take data center performance and security to the next level. Ed Sperling from SemiEngineering will moderate the panel.
12:00pm – 1:45pm PST – Moving Data Faster
With data across the global internet rising at an exponential rate driven by compute-intensive workloads such as AI/ML, higher data rates and more bandwidth are an imperative. Technology experts from the Rambus interface IP business will provide insights and recommendations for implementing HBM2E and GDDR6 high-bandwidth memory, and the latest-generation PCIe 5 interface solution. A live Q&A session will follow the presentations.
2:00pm – 2:45pm PST – Keynote: How Bandwidth is Key to Unlocking Greater AI Performance
Rambus fellow and distinguished inventor, Dr. Steven Woo, will explore the latest developments in AI/ML training and inference. AI/ML performance is advancing at an astonishing rate thanks to purpose-built AI accelerators. Dr. Woo will discuss how emerging memory and system interfaces are key to providing the bandwidth needed for the next generation of AI/ML hardware. A live Q&A session will follow the presentation.
Don’t miss out on the Rambus Design Summit!