At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Found 132 Results
Memory and the IoT
https://www.rambus.com/blogs/memory-and-the-iot/Semiconductor Engineering’s Ed Sperling and Jeff Dorsch recently wrote an article about the challenges of chip design in the age of the IoT. As Sperling notes, this includes sensors, various types of processors, a growing menu of on-chip and off-chip memory types and a long list of I/O and interface IP, chips and chiplets. “There […]
Non-Volatile DDR4 Registering Clock Driver (NVRCD)
https://www.rambus.com/memory-interface-chips/ddr4-dimm-chipset/ddr4-nvrcd/The Rambus NVRCD is the industry’s 1st JEDEC-standard persistent memory register clock driver (NVRCD) in full production for use with NVDIMM-N and emerging NVDIMM-P solutions.
DDR4 on track to hit largest share of DRAM market (by architecture)
https://www.rambus.com/blogs/ddr4-on-track-to-hit-largest-share-of-dram-market-by-architecture/Earlier this month, IC Insights confirmed that DDR4 DRAM gained significant market share in 2016, representing 45% of total DRAM sales. DDR3 DRAM – including low-power versions used in tablets, smartphone and notebook PCs – accounted for 84% of total DRAM sales in 2014 and 76% in 2015. By 2016, DDR4 price premiums had evaporated, […]
Rambus to acquire Inphi’s memory interconnect business
https://www.rambus.com/blogs/rambus-to-acquire-inphis-memory-interconnect-business-2/Rambus has signed a definitive agreement to purchase Inphi’s Memory Interconnect Business for $90M in cash. The acquisition includes all assets of the Inphi Memory Interconnect Business including product inventory, customer contracts, supply chain agreements and IP. According to Rambus CEO Ron Black, the acquisition will further strengthen Rambus’ market position for memory buffer chip […]
When memory and storage converge
https://www.rambus.com/blogs/mid-when-memory-and-storage-converge/Earlier this week, Rambus Chief Scientist Craig Hampel gave a keynote presentation at MemCon 2015 that explored the increasingly blurred lines between memory and storage. As Hampel notes, devices used as memory are typically volatile, byte addressable, directly writable, have deterministic latency and have an endurance greater than 1015 operations. In contrast, storage devices are […]
The 3MB of RAM in William Gibson’s Neuromancer
https://www.rambus.com/blogs/mid-the-3mb-of-ram-in-william-gibsons-neuromancer/Neuromancer, a 1984 cyberpunk novel by William Gibson, was the first winner of the science fiction triple crown: the Nebula Award, the Philip K. Dick Award and the Hugo Award. Marking the beginning of the Sprawl trilogy, the book tells the story of Case, a washed-up computer hacker hired by an enigmatic employer. According to […]
Building bridges with DRAM vendors
https://www.rambus.com/blogs/mid-building-bridges-with-dram-vendors/Analysts at IHS Electronics say Rambus’ change in strategy from intellectual property (IP) licensing house to chipmaker has been “well received” by its customers. “Rambus has announced recently that it would begin developing server memory chipsets for the enterprise and data center server markets in a planned series of devices that are DDR4 JEDEC-compliant,” IHS […]
Future challenges for DDR4 and beyond
https://www.rambus.com/blogs/mid-future-challenges-for-ddr4-and-beyond/Ely Tsern, VP and chief technologist for the Rambus Memory and Interfaces division, has identified five key trends driving future server memory. These include Big Data, additional cores per CPU, a DRAM scaling slowdown, the emergence of storage class memory and the expectation that DDR4 will ultimately reach its speed limit. “Rambus is working with […]
Terabyte Bandwidth Initiative (1TB) Memory Demo
https://www.rambus.com/terabyte-bandwidth-initiative-1tb-memory-demo/Rambus Senior Engineering Manager Arun Vaidyanath demonstrates the latest Rambus test chip running in 3 modes: high-speed differential, GDDR5, and DDR3. Groundbreaking memory technologies developed by Rambus enable signaling at 20 gigabits per second (Gbps) while maintaining best-in-class power efficiency, and up to 12.8 Gbps for single-ended signaling. https://www.youtube.com/watch?v=5y7loaBA2t4&rel=0
FlexMode™ Interface
https://www.rambus.com/flexmode-interface/As chip design and fabrication costs continue to rise with each new process node, the ability to integrate flexible, cost-effective multi-purpose interfaces becomes increasingly valuable. Traditional multi-modal implementations combine the worst-case signal pin count for the functional blocks of the interface for each memory type growing the pin count, area and cost of the interface […]
