Ely Tsern, VP and chief technologist for the Rambus Memory and Interfaces division, has identified five key trends driving future server memory. These include Big Data, additional cores per CPU, a DRAM scaling slowdown, the emergence of storage class memory and the expectation that DDR4 will ultimately reach its speed limit.
“Rambus is working with customers and the industry to determine the most cost-effective ways to address these trends,” he confirmed during a recent presentation at IDF 2015.
“The good news? DDR4 should be capable of scaling to 3.2 – 3.7 Gbps. Simply put, this means DDR4 has ~50% more headroom from systems shipping today.”
According to Tsern, the paradigm required to achieve such speeds within the context of DDR4 includes a maximum of two DIMMS per channel (2DPC), aggressive I/O technologies and fully buffered LRDIMMs optimized for speed. However, DDR4 will ultimately run its course, says Tsern, with applications and systems expected to demand 2x to 3x more bandwidth – a requirement that is unlikely to be met by simply adding more channels.
“The real question? Can DDR architecture be extended to reach 2X again, with speeds up to 6.4+Gbps (at 2DPC)? Of course, a potential DDR5 standard must also support DRAM modules and modules using other memory types, such as NAND Flash and SCM (Storage-Class Memory) on the same channel,” he explained. “Plus, DDR5 should maintain similar economics and infrastructure for low risk industry adoption – while minimizing platform and system cost – vs. DDR4.”
Additional DDR5 requirements outlined by Tsern include minimal CPU and DRAM changes (especially pin count, controller learning), support for both DDP and 3DS, reducing latency and power, as well as the ability to facilitate a smooth transition from DDR4 to DDR5.
“We believe the industry needs to work together on developing next generation DDR solutions, with the goal of doubling current speed with minimal changes,” said Tsern. “Potential DDR5 solution (or directions) include leveraging LRDIMM architecture to support higher frequencies and multiple memory types on the DDR channel; ASIC process scaling; less bus loading; advanced I/O techniques; new data bus topologies and the use of improved, lower swing, power efficient, single-ended signaling and revamped control buses in primary/secondary to remove bottlenecks.”
Rambus, confirms Tsern, already has a DDR5 prototype running at 6.4Gbps (@2 DIMMs per channel).
“In general, memory is an exciting business that faces significant challenges ahead. We at Rambus now have a new focus in server memory with the launch of our R+ DDR4 server memory chipset – RB26 – for RDIMMs and LRDIMMs,” he added. “We’ve also stepped up industry collaboration by joining JEDEC JC-40 and continue to maintain close customer and ecosystem engagements. We plan on delivering high value, JEDEC-standard products for server and datacenter markets. We feel our new chip business extends existing business with a ‘blended’ business model that helps facilitate our engagement with customers and industry on future server solutions.”