At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
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TRNG-IP-76 FIPS-Certified True Random Number Generators Product Brief
https://go.rambus.com/trng-ip-76-product-brief#new_tabThe Rambus TRNG-IP-76 is a FIPS-compliant and certified IP core for True Random Number Generation with an optional post-processor and several internal self-tests. Designed for easy integration into ASICs and SOCs, the 100% digital standard cell based TRNG-IP-76 provides semiconductor designers with an all digital silicon-proven solution that has been thoroughly field tested and deployed […]
Rambus Reports Fourth Quarter And Fiscal Year 2024 Financial Results
https://www.rambus.com/fourth-quarter-and-fiscal-year-2024-financial-results/Delivered record quarterly product revenue of $73.4 million, up 11% sequentially and 37% year over year Generated record annual cash from operations of $230.6 million for 2024, up 18% year over year Extended patent license agreement with Micron through 2029 SAN JOSE, Calif. – February 3, 2025 – Rambus Inc. (NASDAQ:RMBS), a provider of industry-leading chips and […]
CRNG-IP-77 (True Random Number Generator)
https://www.rambus.com/security/crypto-accelerator-cores/trng-ip-77/CRNG-IP-77 FIPS-Certified True Random Number Generators Contact Us The CRNG-IP-77 is a Fast NIST ESV certified, FIPS (SP800-90A/B/C) Cellular Automata-based True Random Number Generator IP core for True Random Number Generation (TRNG) with an optional post-processor and several internal self-tests. Designed for easy integration into ASICs and SOCs, the 100% digital standard cell based CRNG-IP-77 […]
Revolutionizing Power Efficiency in PCIe 6.x: L0p and Flit Mode in Action
https://www.rambus.com/blogs/revolutionizing-power-efficiency-in-pcie-6x-l0p-and-flit-mode-in-action/The latest PCIe 6.x specification brings groundbreaking advancements in power efficiency and performance optimization. In this technical demonstration, Senior Principal Application Engineer Julien Eydoux showcases two features of Rambus’ PCIe 6.x Controller: L0p mode and FLIT mode operation. Dynamic Power Management The demonstration reveals how L0p mode enables dynamic lane scaling without compromising performance. This […]
Matt Jones
https://www.rambus.com/leadership/matt-jones/Matt Jones Senior Vice President & General Manager of Silicon IP Matt Jones joined Rambus in 2019 and currently serves as the Senior Vice President and General Manager of Silicon IP at Rambus. He is responsible for the development and growth of the company’s silicon IP products, driving high-performance, secured memory and interconnect architectural innovation in […]
Rami Sethi
https://www.rambus.com/leadership/rami-sethi/Rami Sethi Senior Vice President & General Manager of Memory Interface Chips Rami Sethi is Senior Vice President and General Manager of the Memory Interface Chip Business Unit for Rambus, where he has full P&L responsibilities and manages the related business and engineering organizations. Before joining Rambus, Rami was Corporate Vice President and General Manager […]
Rambus at DesignCon
https://www.rambus.com/designcon/Rambus @ DesignCon 2025 Join Rambus for a day of technical sessions at DesignCon on January 29, 2025. Hear from our experts on the technologies that are set to shape the future of data centers and high-performance systems, and discover how our cutting-edge memory, interconnect and security IP enables today’s most challenging computing, edge, automotive […]
Rambus and Micron Technology Extend Patent License Agreement
https://www.rambus.com/rambus-and-micron-technology-extend-patent-license-agreement/Five-year agreement extends product collaboration and enables broad access to Rambus innovations SAN JOSE, Calif. – Dec. 10, 2024 – Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced it has extended the term of its comprehensive patent license agreement with Micron Technology, Inc. for an […]
Breaking Through The Generative AI Memory Wall
https://www.forbes.com/councils/forbestechcouncil/2024/11/21/breaking-through-the-generative-ai-memory-wall/#new_tabThe term “memory wall” was first coined in the 1990s to describe memory bandwidth bottlenecks that were holding back CPU performance. The semiconductor industry helped address this memory wall through DRAM architecture innovations, rapidly increasing memory bus widths and data rates, and better process technologies that made faster memory and interfaces manufacturable. The torrid pace […]
Ask the Experts: DDR5 MRDIMMs
https://www.rambus.com/ask-the-experts-ddr5-mrdimms/https://youtube.com/watch?v=dNQthJ6Xnt4%3Fsi%3DmlHdcwBc8rXyK9jX John Eble, Vice President of Product Marketing for Memory Interface Chips at Rambus, discusses the new MRDIMM (Multiplexed Registered DIMM) DDR5 memory module architecture. Key takeaways include: Enhanced DDR5 Architecture Doubled Bandwidth Increased DRAM Capacity New Memor Interface Chips Future Roadmap
