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3DES-IP-16 3DES ECB/CBC Accelerators

The 3DES-IP-16 (EIP-16) is IP for accelerating the AES symmetric cipher algorithm (FIPS-46/81 – SP800-IP-20), supporting single Des and triple DES in ECB, CBC, CFB and OFB modes up to 4 Gbps @ 800MHz. Designed for fast integration, low gate count and full transforms, the 3DES-IP-16 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high speed crypto pipelines.

3DES family of accelerators.

Available in three configurations / performance grades.

Library element for security packet engines.

How the 3DES-IP-16 3DES ECB/CBC Accelerators work

The 3DES-IP-16 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the 3DES-IP-16 is the cipher core embedded in all IPsec protocol aware security engines. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance for any object sizes ranges up to 4 Gbps depending on the configuration and area. Gate count is between 9K and 15K gates depending on the configuration. Multiple 3DES-IP-16 cores can be cascaded.

Rambus also offers the AES-IP-39 that supports AES modes and can be provided with countermeasures including ones against side-channel attacks and fault injection attacks.

TDES-IP-16 legacy 3DES and DES Accelerators
TDES-IP-16 legacy 3DES and DES Accelerators
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Anti-Tampering Technologies

The design of chip anti-tamper protection needs to adapt and scale with rising threats. Adversaries range from high school hackers to well-funded state actors. Given the threats, it’s useful to think about anti-tamper countermeasures as a hierarchy of safeguards that parallel the type, effort and expense of attacks. Watch this webinar to learn the eleven kinds of tampering attacks and their required skills and resources, and countermeasures for each of these attacks.

3DES-IP-16 3DES ECB/CBC Accelerator Information

Key benefits:

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support
 

Features:

  • Wide bus interface (64-bit data, 192-bit keys, 64-bit IV) or 32 bit register interface.
  • Key sizes: 64 and 192 bits.
  • Feedback modes: ECB, CBC, OFB (1, 8 and 128 bit), 
CFB (1, 8 and 128 bit).
  • Low Speed, Medium Speed, High Speed versions.
  • Fully synchronous design.
 

Alternatives:

  • AES-IP-32 AES ECB accelerators
  • AES-IP-36 AES ECB/CBC/CTR accelerators
  • AES-IP-37 AES Key Wrap accelerators
  • AES-IP-38 AES XTS/GCM accelerators
  • AES-IP-39 AES ECB/CBC/CTR/CCM/GCM accelerators
Introduction to Side-Channel Attacks eBook

Introduction to Side-Channel Attacks

Side-channel attacks conducted against electronic gear are relatively simple and inexpensive to execute. Such attacks include simple power analysis (SPA) and Differential Power Analysis (DPA). As all physical electronic systems routinely leak information, effective side-channel countermeasures should be implemented at the design stage to ensure protection of sensitive keys and data.

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