Poly-IP-53 (EIP-53) is IP for accelerating the Poly1305 hash-based message authentication algorithm (RFC7539), supporting the NIST MAC mode up to 6.4 Gbps @ 450MHz. Designed for fast integration, low gate count and full transforms, the Poly-IP-53 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high speed crypto pipelines.
Poly1305 family of accelerators
Available in several configurations / performance grades
Supporting TLS1.3 IoT HomeKit
The Poly-IP-53 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the Poly-IP-53 is the cipher core embedded in the Vault-IP-140 platform security engines providing support for TLS1.3 and HomeKit IoT applications (Poly1305 is also available as software implementation in the VaultIP core). The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.
Sustained performance for any object sizes ranges from 1 to 6.4 Gbps depending on the configuration and area. Gate count is around 50K gates depending on the configuration.
Rambus also offers the required ChaCha20 cipher to match the Poly1305 algorithm to match the HomeKit.
The design of chip anti-tamper protection needs to adapt and scale with rising threats. Adversaries range from high school hackers to well-funded state actors. Given the threats, it’s useful to think about anti-tamper countermeasures as a hierarchy of safeguards that parallel the type, effort and expense of attacks. Watch this webinar to learn the eleven kinds of tampering attacks and their required skills and resources, and countermeasures for each of these attacks.
Side-channel attacks conducted against electronic gear are relatively simple and inexpensive to execute. Such attacks include simple power analysis (SPA) and Differential Power Analysis (DPA). As all physical electronic systems routinely leak information, effective side-channel countermeasures should be implemented at the design stage to ensure protection of sensitive keys and data.