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SNOW-IP-46 3GPP SNOW 3G Accelerators

The SNOW-IP-46 (EIP-46) cipher accelerators implement the specification of the 3GPP Confidentiality and Integrity Algorithms as specified by 3GPP and ETSI. Designed for fast integration, low gate count and full transforms, the SNOW-IP-46 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high speed SoCs for base stations or other equipment requiring 3GPP support.

3GPP Snow 3G family of accelerators.

Available in three configurations / performance grades.

Targeting Base Station designs.

How the SNOW-IP-46 3GPP SNOW 3G Accelerators work

The SNOW-IP-46 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the SNOW-IP-46 is the cipher core embedded in some PacketEngine-IP-97/196/197 protocol aware security engines. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance for any object sizes ranges from 4 to 30 Gbps depending on the configuration, area and frequency. Gate count is 20K to 40K gates depending on the configuration. Supported modes: UEA2, UIA2, 128-EEA1 and 128-EIA1

Rambus also offers accelerators for the other 3GPP algorithms.

SNOW-IP-46 3GPP SNOW3G Accelerators
SNOW-IP-46 3GPP SNOW3G Accelerators
Watch Anti-Tampering Technologies Webinar

Anti-Tampering Technologies

The design of chip anti-tamper protection needs to adapt and scale with rising threats. Adversaries range from high school hackers to well-funded state actors. Given the threats, it’s useful to think about anti-tamper countermeasures as a hierarchy of safeguards that parallel the type, effort and expense of attacks. Watch this webinar to learn the eleven kinds of tampering attacks and their required skills and resources, and countermeasures for each of these attacks.

SNOW-IP-46 Information

Key benefits:

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support
 

Features:

  • Wide bus interface (32-bit data, 128-bit keys) or 32-bit register interface
  • Includes key scheduling hardware
  • Supported modes: UEA2, UIA2, 128-EEA1 and 128-EIA1
  • Fully synchronous design
  • Low Speed, High Speed versions
Introduction to Side-Channel Attacks eBook

Introduction to Side-Channel Attacks

Side-channel attacks conducted against electronic gear are relatively simple and inexpensive to execute. Such attacks include simple power analysis (SPA) and Differential Power Analysis (DPA). As all physical electronic systems routinely leak information, effective side-channel countermeasures should be implemented at the design stage to ensure protection of sensitive keys and data.

Don’t miss out on the Rambus Design Summit on October 8th!