Rambus intelligent security protocol engines deliver the benefits of throughput acceleration in combination with significant CPU offload by performing complete protocol transformations. The Multi-Protocol Engines offer acceleration of IPsec, SSL/TLS/DTLS, MACsec and basic hash and crypto operations at speeds from 100 Mbps to 100 Gbps in architectures ranging from the traditional Look-Aside engines attached to an AMBA bus system, to more sophisticated and powerful inline packet engines.
The Multi-protocol engines support all common symmetric FIPS compliant algorithms, 3GPP algorithm, Chinese algorithm and various additional optional algorithms for specific applications. The IPs integrate with various open source data planes, such as DPDK and ODP as well as directly with the Linux Crypto APIs.
|Protocol-IP-93||Accelerate IPsec, SSL/TLS up to 1 Gbps, including TLS 1.2 and 1.3. This protocol-aware packet engine with Look-Aside interface is well suited for acceleration of the TLS packet processing in IoT devices with cloud access, low power constraints and/or secure boot acceleration. Designed for fast integration and low-gate count requirements.|
|Protocol-IP-97||Accelerate IPsec, SSL, TLS, DTLS, 3GPP, and MACsec up to 5 Gbps with this protocol-aware packet engine with Look-Aside interface. Designed for fast integration, low-gate count, complete L3 packet transforms, performing 2 Gbps full-duplex for any packet size.|
|Protocol-IP-196||Accelerate IPsec, SSL, TLS, DTLS, 3GPP and MACsec up to 10 Gbps with this protocol-aware packet engine with Look-Aside interface. Designed for fast integration, maximum CPU offload, full transforms and easy integration into SoC designs with full Virtualization support. Embedded caches and latency compensation guarantee throughput is maintained under extreme latency conditions.|
|Protocol-IP-197||Accelerate IPsec, SSL, TLS, DTLS (CAPWAP), 3GPP and MACsec up to 100 Gbps with protocol-aware packet engine with classifier and Look-Aside and Inline streaming interfaces. Designed for fast integration, maximum CPU offload, full transformation offload with classification. Integrates smoothly into complex SoCs with full virtualization support. Embedded caches and latency compensation to guarantee throughput is maintained under extreme latency conditions.|
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