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Download this product brief to learn more about the Rambus CryptoManager Root of Trust RT-1664 for U.S. Defense mission-critical applications.
[Live on 08/27 at 9am PT] Join Lou Ternullo from Rambus along with Yiannis Nikolakopoulos from ZeroPoint as they discuss a solution that addresses the evolving requirements of hyperscale data centers, as outlined in open compute specifications.
Exceeded expectations for Q2 revenue and earnings Achieved record quarterly product revenue of $81.3 million, up 43% year over year Generated record quarterly cash from operations of $94.4 million SAN JOSE, Calif. – July 28, 2025 – Rambus Inc. (NASDAQ:RMBS), a provider of industry-leading chips and IP making data faster and safer, today reported financial […]
The tutorial will focus on DRAM architecture, specifically looking at design tradeoffs and subsequent impact to the overall system performance, power, cost and reliability. The tutorial will cover the following topics.
From the first monochrome mobile displays to today’s ultra-high-definition automotive dashboards and immersive AR/VR headsets, MIPI technology has quietly become the backbone of modern data connectivity. Let’s explore how MIPI standards have evolved, the markets they serve, and why Rambus is at the forefront of this transformation. Table of Contents: What does MIPI stand for? […]
Quantum Safe Core Library Contact Us Rambus Quantum Safe Core Library offers cryptographic algorithms for the PQC (Post Quantum Cryptography) era with a focus on minimal resource usage and dependencies. Quantum Core Library is a ‘bare-metal’ software implementation with no OS dependencies and low footprint. The library does not include ‘classic’ or ‘traditional’ algorithms making […]
SphincsLib Contact Us Rambus SphincsLib is a standalone ‘bare metal’ software library, which implements the SLH-DSA FIPS 205 standard. SphincsLib provides key generation, signature generation and signature verification for SLH-DSA. The library implements the hashing operations in software but can be integrated with a hardware core for acceleration. SphincsLib is optimized for minimal footprint and […]
As per socket compute density increases, the amount of directly accessible, low-latency memory bandwidth and capacity to adequately feed data to the multiple cores needs to scale accordingly. Scaling memory bandwidth by increasing raw DRAM component bandwidth or by increasing the number of memory channels has challenges and is reaching limits. JEDEC has unveiled the […]
Download the product brief to learn how the Rambus PMIC5100 (P1535Gxx) enables client UDIMMs, CUDIMMs, SODIMMs and CSODIMMs. With the Rambus Client Clock Driver and SPD Hub ICs, it comprises a complete memory interface chipset for client DIMMs.
Download the product brief to learn more about the Rambus DDR5 Multiplexed Registering Clock Driver (MRCD) and Multiplexed Data Buffer (MDB).