In a new webinar, Scott Best, the director of anti-counterfeiting products and technologies in the Security business at Rambus, discusses how the design of anti-tamper protection needs to recognize and scale with rising threats. Adversaries range from high school hackers to well-funded state actors. As such, Scott details how it’s useful to think about anti-tamper countermeasures as a hierarchy of safeguards that parallel the type, effort and expense of attacks.
The categories of tampering attacks include:
- Non-invasive: usually passive, the attacker monitors the operation of the chip but does not try to modify its normal operation
- Semi-invasive: an attacker induces electrical failures within the chip and monitors the resulting effects
- Fully invasive: often destructive attacks where an attacker bypasses shields, modifies signal connectivity, etc.
- Reverse engineering: destructive analysis of the chip aimed at obtaining the non-volatile memory (NVM) contents or recovering netlist algorithms
One of the values of thinking about the threat in this hierarchical manner is that it aids in planning the anti-tamper defenses for a chip appropriate to the motivation and funding of the attacker. For instance, if a chip is going into a military platform that could fall into the hands of a state-actor adversary, then it should be hardened against the full range of tampering attacks.
Within this context, Scott details eleven categories of tampering attacks ranging from protocol and software attacks to NVM extraction attacks. For each category, he lays out the resources and skills adversaries employ and the countermeasures to counter these attacks. It’s a great road map for chip makers planning the anti-tamper safeguards they need to incorporate into their designs. You can listen to a replay of the full webinar here.