Semiconductor scaling has been a boon without equal to the world of computing. But with the slowing of Moore’s Law, the industry has had to pursue new architectural solutions to continue to push the pace of computing performance. The seismic shift has been the move to heterogenous computing architectures. This has witnessed a profusion of purpose-built silicon as we’ve entered the “Accelerator Age.”
Compute Express LinkTM (CXLTM) technology is a key enabler of heterogenous computing as it allows cache coherent access and sharing of memory resources between main processors (hosts) and accelerators. It also provides for memory expansion, and the pooling of memory resources among hosts for new disaggregated architectures in data centers. Disaggregation promises to provide greater memory utilization efficiency and improved TCO.
As a leader in chips and IP that make data faster and safer, Rambus recognized the critical importance of CXL technology to the future of the data center launching the CXL Memory Interconnect Initiative in June of last year. Rambus acquired PLDA and AnalogX in no small part to provide key digital controller and PHY IP for the initiative. Now Rambus has closed the acquisition of Hardent to further accelerate the development of CXL solutions.
Hardent is a leading electronic design company, and the team of engineers there bring world-class silicon design, verification, compression, and Error Correction Code (ECC) expertise. The design talent from Hardent, a company with a 20-year track record of success in semiconductors, will augment the world-class engineering team at Rambus. CXL represents a once-in-a-decade opportunity for new chip and IP solutions that accelerate next-generation data centers, and we’re anxious to have the Hardent team on board to help us in this pursuit.
Sam Sanyal says
In HSA, the CPU is not the Central Processing Unit anymore, the tasks are distributed among muti-ISA devices environments. The data inconsistency is definitely not acceptable, a cache coherence problem. Cache coherence schemes are supposed to help to avoid this problem by maintaining a uniform state for each cached block of data. The question is can CXL address Uniform Memory Access (UMA) and Non-Uniform Memory Access (NUMA) in different ISA/HSA environments?
I bring this up since you mentioned “Compute Express LinkTM (CXLTM) technology is a key enabler of heterogeneous computing …”. Has anyone proven it with the implementation of CXL in CPU & GPU environments where GPUs have thousands of cores (e.g NVidia A100 or H100) and CPU have 10s of cores? I wonder how difficult it will be to synchronization of memory access!