CXL Controller with Zero Latency IDE: You Can’t Do Better Than Zero

The virtuous cycle of data holds that as volume increases, the value increases. More volume requires faster processing and faster links. More value demands that computing and connecting be secure. That’s why the Compute Express Link™ (CXL) standard specifies that its speedy links be protected by Integrity and Data Encryption (IDE). But if the implementation of IDE introduces latency overhead, then you’re operating at cross purposes where performance is sacrificed for security.

How about instead, you have your cake and eat it too? Rambus has introduced a CXL 2.0 controller with integrated IDE that has zero latency for the CXL.mem and CXL.cache protocols. That means you can get all the benefits of CXL 2.0’s 32 GT/s signaling rate, and all the security of IDE with no hit to performance. Pairing the controller with the Rambus CXL 2.0/PCI Express® 5.0 PHY comprises a complete CXL 2.0 interconnect subsystem for implementation in SoCs.

When it comes to latency, you can’t do better than zero. So, we’ll mark this down as a world record that can never be broken. You can get all the technical details on the CXL 2.0 controller with integrated IDE here and on the CXL 2.0/PCI Express 5.0 PHY here.