The Rambus PCI Express (PCIe) 5.0 and Compute Express Link (CXL) PHY is a low-power, area-optimized, silicon IP core designed with a system-oriented approach to maximize flexibility and ease of integration. It delivers up to 32 GT/s data rates in performance-intensive applications for artificial intelligence (AI), data center, edge, 5G infrastructure and graphics. With the Northwest Logic Expresso 5.0 controller core it comprises a complete PCIe 5.0 SerDes subsystem. Alternatively, it can be integrated with PIPE 5.2-compliant 3rd-party controllers. The PCIe 5 SerDes PHY supports PCIe 5.0, 4.0, 3.0 and 2.0, and has full support for manufacturability.
The Rambus PCIe 5.0 PHY with the Expresso 5.0 digital controller comprise a high-performance serial link subsystem. Optimized for power in challenging, high-loss channels, our PCIe 5.0 interface solution is ideal for performance-intensive AI, data center, edge, 5G infrastructure and graphics applications.
The PHY consists of a PMA hard macro that supports PCIe 5.0, 4.0, 3.0 and 2.0 protocols and a physical coding sublayer (PCS) soft macro for PCIe that is PIPE 5.2 compliant. Co-verified with the Northwest Logic Expresso 5.0 digital controller, the PHY can also be integrated with 3rd-party PIPE 5.2-compliant controllers.
Designed with a minimal set of broadside controls, the PHY is configurable in x2, x4, x8 and x16 lane configurations with bifurcation support. This gives the PHY improved flexibility and support for a wide range of applications. Multi-tap transmitter and adaptive receiver equalization supports more than 36dB of channel insertion loss.
The PCIe 5 SerDes PHY is available on an advanced 7nm FinFET process node.
Comprehensive Chip and System Design Reviews
Engineering Design Services:
|Protocol||Data Rate (Gbps)||Application|
|PCIe 2.0||5||High bandwidth peripherals and graphics|
|PCIe 3.0||8||Servers, storage, networking devices|
|PCIe 4.0||16||Servers, storage, networking devices|
|PCIe 5.0||32||AI, servers, storage, networking, 5G infrastructure|
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