Designed with a minimal set of broadside controls, the PHY is configurable in x2, x4, x8 and x16 lane configurations with bifurcation support. This gives the PHY improved flexibility and support for a wide range of applications. Multi-tap transmitter and adaptive receiver equalization supports more than 36dB of channel insertion loss.
The PCIe 5 SerDes PHY is available on an advanced 7nm FinFET process node.
The PCI Express® (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), require the new level of performance of PCI Express 5.0.
|Protocol||Signaling Rate (GT/s)||Application|
|PCIe 2.0||5||High bandwidth peripherals and graphics|
|PCIe 3.0||8||Servers, storage, networking devices|
|PCIe 4.0||16||Servers, storage, networking devices|
|PCIe 5.0||32||AI, servers, storage, networking, 5G infrastructure|
Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation.