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Interface IP

PCIe 5.0 SerDes PHY

The Rambus PCI Express (PCIe) 5.0 and Compute Express Link (CXL) PHY is a low-power, area-optimized, silicon IP core designed with a system-oriented approach to maximize flexibility and ease of integration. It delivers up to 32 GT/s data rates in performance-intensive applications for artificial intelligence (AI), data center, edge, 5G infrastructure and graphics. With the Northwest Logic Expresso 5.0 controller core it comprises a complete PCIe 5.0 SerDes subsystem. Alternatively, it can be integrated with PIPE 5.2-compliant 3rd-party controllers. The PCIe 5 SerDes PHY supports PCIe 5.0, 4.0, 3.0 and 2.0, and has full support for manufacturability.

How the PCIe 5.0 Interface Works

The Rambus PCI express 5 PHY with the Expresso 5.0 digital controller comprise a high-performance serial link subsystem. Optimized for power in challenging, high-loss channels, our PCIe 5.0 interface solution is ideal for performance-intensive AI, data center, edge, 5G infrastructure and graphics applications.

The PHY consists of a PMA hard macro that supports PCIe 5.0, 4.0, 3.0 and 2.0 protocols and a physical coding sublayer (PCS) soft macro for PCIe that is PIPE 5.2 compliant. Co-verified with the Northwest Logic Expresso 5.0 digital controller, the PHY can also be integrated with 3rd-party PIPE 5.2-compliant controllers.

PCIe 5.0 Interface Subsystem Example
PCIe 5.0 Interface Subsystem Example

Designed with a minimal set of broadside controls, the PHY is configurable in x2, x4, x8 and x16 lane configurations with bifurcation support. This gives the PHY improved flexibility and support for a wide range of applications. Multi-tap transmitter and adaptive receiver equalization supports more than 36dB of channel insertion loss.

The PCIe 5 SerDes PHY is available on an advanced 7nm FinFET process node.

Solution Offerings

  • Complete SerDes subsystem solution with co-validated Expresso 5.0 digital controller core from Northwest Logic, a Rambus company
  • PIPE 5.2-compliant interface for integration with 3rd-party controllers
  • PHY supports CXL interface specification
  • Duplex lane configurations of x1, x2, x4, x8 and x16 with bifurcation support
  • Flexible ASIC clocking
  • Multi-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
  • Continuous-time linear equalizer (CTLE) and multi-tap decision feedback equalizer (DFE) capable of compensating more than 36dB of channel insertion loss across PVT
  • Support for transmitter and receiver spread spectrum clocking (SSC) to meet FCC regulations for electro-magnetic interference (EMI)
  • Expandable register interface enabling communication with multiple PMAs and PCS-BIST soft macros
  • Built-in self test (BIST) with ATPG and AC/DC Boundary scan support
  • Built-in per-channel PRBS-7, 9, 11, 15, 23, 31 and user-defined pattern generation and checking for standalone loopback testing
  • In-situ real-time monitoring and receive data eye schmoo enabling PCIe RX margining feature
  • Operation across a wide temperature range (-40 C to +125 )
  • Automatic calibration of key circuits to maximize performance and yields
  • PMA Hard Macro
    • Verilog models
    • LEF abstracts (.lef)
    • Timing models (.lib)
    • CDL netlists (.cdl)
    • ATPG models
    • IBIS-AMI models
    • GDSII layout
    • DRC & LVS reports
  • PCS-BIST Soft Macro
    • RTL model
  • Datasheet
  • SoC Integration guide

Comprehensive Chip and System Design Reviews

  • Kickoff/Program Review
  • Floor plan Review
  • Test/Characterization Plan Review
  • Package Design Review
  • Board Design Review
  • Final Chip Integration Review
  • Bring-up and Test Review

Engineering Design Services:

  • Package design
  • System board layout
  • Statistically-based signal and power integrity analysis

Protocol Compatibility

ProtocolData Rate (Gbps) Application
PCIe 2.05High bandwidth peripherals and graphics
PCIe 3.08Servers, storage, networking devices
PCIe 4.016Servers, storage, networking devices
PCIe 5.032AI, servers, storage, networking, 5G infrastructure
SerDes Signal Integrity Challenges at 28Gbps and Beyond

SerDes Signal Integrity Challenges at 28Gbps and Beyond

Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation. 


Phase Interpolator-Based CDR

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.