We met recently with Shane Rau, Research Vice President at IDC, for a webinar to discuss the market and technology trends surrounding the transition from DDR4 to DDR5.
We were lucky enough to get a few minutes with Shane and ask a few questions beyond the webinar. Read the full interview below.
Interview with Shane Rau
1. Give us your perspective why the time between generations of main memory is getting longer.
Shane Rau, IDC: “While being an adaptable technology, the increasing TAM of DRAM means more folks must be involved in its standardization. For example, an ecosystem or organizations has worked on DDR5 for more than five years, such as JEDEC, memory controller vendor, CPU and GPU vendors, DRAM chip vendors, module vendors, buffer vendors, and system makers. Further, even if all these folks agree on the standard, the launch of the memory has to time with market need for its benefits which means overcoming initial cost premium and additional complexity. In the case of DDR5, originally scheduled to launch in 2018, beyond those issues of enabling the ecosystem and aligning with the market, it has also faced the pandemic, which roiled supply chains and the ability of the market to absorb the new technology.”
2. From a priority order, how do the needs of more bandwidth, more capacity and lower latency stack up for DDR5 and why?
Shane Rau, IDC: “Of course, end customers vary in their priorities for adopting a new technology like DDR5. However, from my view as a market analyst, putting more and more memory—capacity—nearer to the processor has been the top priority of the market through DDR4 and now DDR5. Yet, as the average capacity of DRAM in a system has grown, the harder it has gotten for the processor to get requests into and out of DRAM, thus the need for more speed (bandwidth) and so reduced time to answers (latency).”
Interested in hearing more from Shane? More capacity and more bandwidth: DDR5 memory enables next-generation data centers is now available to watch on-demand! Click here to watch the webinar.