Part 1: DRAM goes cryogenic
This entry was posted on Monday, July 10th, 2017.
Rambus Chief Scientist Craig Hampel recently spoke with Ed Sperling of Semiconductor Engineering about the power benefits and performance advantages of running DRAM at extremely low cryogenic temperatures (below minus−180 °C or 93.15 kelvin).
“When operating fairly conventional technologies based on CMOS in that domain, a lot of interesting things begin to happen. One of the bigger challenges in scaling CMOS has been leakage. Leakage goes to zero really quickly [in a cryogenic environment] and begins to reduce its ability to be a problem that affects [issues] such as DRAM refresh – and in many cases the static power consumed by a circuit,” he explains.
“Down around 4 kelvin (and for some materials as low as 7 kelvin) you have this phenomenon where effectively the wires super conduct. [This] lets you sync signals over longer distances with extremely small amounts of energy, [as] the power consumption for those circuits approaches zero to communicate on wires and the performance of those circuits also approaches that of an optical interconnect.”
Cryogenic computing, says Hampel, is also interesting in the context of the quantum realm, where most of the known approaches to achieving qubits require extremely low thermal noise and extremely low temperatures. In fact, some machines are targeted at the millikelvin range, effectively making these systems some of the coldest places in the known universe.
“[Let’s] take a look at [current] memory subsystems [operating at] conventional temperatures. There’s SRAM and DRAM, solid state storage flash and there’s also some emerging memories [such as] phase change materials (PCM) and RRAM (ReRAM),” he continues. “They [consume] a certain amount of power, with power scaling and density remaining a significant problem. The power consumed by these circuits is not really going down very quickly anymore. However, at 77 kelvin some interesting things [begin happening with DRAM]. For example, on-chip leakage decreases rapidly, so in some respects, DRAM becomes a non-volatile device at this temperature.”
In addition, says Hampel, transistor performance increases substantially, allowing engineers to decrease the threshold voltage at the same performance point and then decrease the overall operating voltage of the device. Moreover, when the temperature reaches the superconducting domain (4-7 kelvin), depending on the materials, there is no energy loss, while the transport time of an electron approaches the speed of light.
“There are some really interesting opportunities to [design] compute and memory subsystems down at [these] extremely low temperatures. [This requires] high-performance interfaces to take advantage of DRAM [residing] at slightly higher temperatures. There are a number of things needed [to accomplish] this, [including] new materials, circuits, architectures, design and interfaces.”
Hampel also noted that one of the greatest challenges in terms of planar density for DRAM is the size of the capacitor – which is the minimum size of the bit cell. The size of that capacitor, he explains, is driven by how much leakage, capacitance and charge it needs to store a bit. Lower temperatures offer the potential to more easily build high-capacity DRAMs. Similarly, cryogenic temperatures or below can also benefit spatial density, or three-dimensional density.
“The reason you can’t stack DRAM on top of DRAM on top of DRAM and build DRAM in a cube is [because] of [the need for] thermal dissipation. As we get this significant increase in power efficiency, we can potentially build more 3D density DRAMs as well, [while as] the wires get shorter the delays get shorter. You get a lot of additional benefits from spatially dense DRAM and more dense computing systems,” he added.
Read Part 2: DRAM goes cryogenic here.