The case for cold DRAM in the data center
This entry was posted on Thursday, October 5th, 2017.
Cryogenic, superconducting digital processors offer the promise of significantly reduced operating power for server-class computing systems. This is due to the exceptionally low energy per operation of Single Flux Quantum circuits built from Josephson junction devices operating at the temperature of 4 Kelvin. However, no suitable same-temperature memory technology yet exists to complement these SFQ logic technologies. Although potential memory technologies are in the early stages of development, it will take years for them to reach the cost per bit and capacity capabilities of current semiconductor memory.
In the interim, Rambus Labs has published a paper that explores how cold memories built from CMOS DRAM and operating at 77K can support superconducting processors at low cost-per-bit, and can even do so today. The paper, titled “Do Superconducting Processors Really Need Cryogenic Memories? The Case for Cold DRAM,” was presented at the third International Symposium on Memory Systems in Alexandria, VA, on October 2-5, 2017.
“This paper is the first work to be published in the context of Rambus’ ongoing collaboration with Microsoft to develop prototype systems that optimize memory performance in cryogenic temperatures,” explained co-author Kenneth Wright, Senior Director in Rambus Lab. “It discusses the pros and cons of four different technologies (or options) for building a cold memory system to support a superconducting coprocessor: new memory @4K, new memory + CMOS @4K, DRAM @4K, and DRAM @77K.”
According to Sally A. McKee, Professor at Chalmers University of Technology and Memory Architecture Researcher in Rambus Labs, employing CMOS support circuits with 4K cryogenic memory technology means that memory devices do not have to be directly compatible with the processor’s SFQ circuits. Nevertheless, it does so at a high price: the energy costs of the emerging memory with CMOS support circuits are dominated by the CMOS, giving this design point few advantages over a CMOS DRAM system running at 4K. In addition, while a 4K DRAM system provides low access latency by locating the memory close to the processor, this configuration inevitably incurs high cooling costs.
Placing DRAM in a 77K temperature domain, says McKee, delivers most of the benefits of the 4K system (negligible leakage, large capacity, and low cost) with significantly lower cooling costs.
“We chose 77K because liquid nitrogen is inexpensive and because the infrastructure for it is widely developed, making this an obvious target domain for optimizing energy expenditure as well as capital and operating expenses,” McKee told Rambus Press. “Our simulations of DRAM component circuits operating at 77K reveal no significant functional issues, and initial experiments with commercially available devices indicate that cold temperatures do not prevent operation, and they provide retention and power benefits. Perhaps most importantly, we’ve concluded that cold memories built from CMOS DRAM – and operating at 77K – are currently capable of supporting superconducting processors at a low cost-per-bit.”
In addition to the above-mentioned memories, the paper explores the potential use of resistive RAM (RRAM) and spin torque transfer magnetic RAM (STT-MRAM) in a cold computing environment. However, one of the known issues for both these emerging technologies is that their write energy per bit is much higher than DRAM – which acts as a distinct disadvantage for cryogenic operation.
“In cryogenic Hafnium Oxide-based RRAMs, power consumption goes up as temperature decreases because the SET and RESET voltages increase slightly. In addition, the oxygen ion thermal energy decreases, meaning the oxygen needs a higher electrical field to overcome the barrier to form or disrupt the conductive filament,” Eric Linstadt, Principal Engineer at Rambus and paper co-author, elaborated. “Meanwhile, cryogenic operation is also unlikely to significantly reduce power draw for spin torque transfer magnetic RAM because STT-MRAM is based upon tunneling junctions and there is no inherent voltage scaling. Although the lower thermal energy means cell currents and areas can be reduced (offering a potential decrease in read and write power and enabling further scaling of the access transistor dimensions), this reduces the thermal assistance that initiates switching, which increases cycle times and/or write bit error rates.”
Interested in learning more about cold DRAM in the data center? Written by Fred Ware, Liji Gopalakrishnan, Eric Linstadt, Sally A. McKee, Thomas Vogelsang, Kenneth L. Wright, Craig Hampel and Gary Bronner, the paper “Do Superconducting Processors Really Need Cryogenic Memories? The Case for Cold DRAM,” can be downloaded here.