Rambus has joined the RISC-V Foundation as a founding member. The organization is dedicated to managing and promoting the adoption of the RISC-V hardware architecture standard throughout the semiconductor market. With this announcement, Rambus joins a coalition comprising dozens of major industry players, including Google, Oracle, Western Digital and BAE Systems.
“RISC-V is a perfect example of the exciting ways in which the semiconductor industry is evolving and embracing new models, including open source standards,” said Martin Scott, senior vice president and general manager of the Security Division at Rambus. “Rambus is dedicated to pushing our industry forward through innovative and creative thinking, and we’re proud to be part of the group of companies shepherding the development and growth of this new semiconductor ecosystem.”
By signing on as a founding member of the RISC-V Foundation, Rambus will work alongside other coalition members, calling upon the company’s decades of expertise to foster the growth and promotion of the RISC-V architecture, while ensuring it meets the demands of a rapidly growing and changing technology sector.
As we’ve previously discussed on Rambus Press, RISC-V is an instruction set architecture designed as an open standard. Based on years of research conducted at the University of California, Berkeley, the RISC-V standard is designed to be open and flexible, supporting a wide variety of academic and industry use cases. By embracing standards such as RISC-V, the semiconductor industry can find new efficiencies and revenue opportunities – while creating an ecosystem that is favorable to developers and manufacturers.
It should be noted that RISC-V has gained significant momentum over the past year. Indeed, engineers at ETH Zurich and the University of Bologna recently debuted the 32-bit PULPino, an open-source microprocessor based on RISC-V architecture. The PULPino – taped out as a 65nm ASIC – is now available for RTL simulation and FPGA mapping.
Meanwhile, an R&D division of the Indian government is on track to develop its very first 64-bit microprocessor based on the RISC-V instruction set. In addition, a separate team of designers at IIT Madras has been working for more than two years on a family of 32- and 64-bit open source processors based on RISC-V, known as Shakti. According to EE Times, the Shakti project now includes plans for at least six microprocessor designs along with fabrics and an accelerator chip.
On the software side, engineers at Genode unveiled new support for RISC-V CPU architecture. For the uninitiated, the Genode Framework can perhaps best be described as a tool kit for building highly secure special-purpose operating systems. It is capable of scaling from embedded systems with as little as 4 MB of memory to highly dynamic general-purpose workloads. According to Norman Feske of OS News, RISC-V is a “possible answer” to the call for more trustworthy hardware. Indeed, such a prospect is what motivated the Genode project to take a closer look at the open source ISA.
As recently noted in “Charting a New Course for Semiconductors,” the success of open-source software – as opposed to a closed, walled-garden approach – has set an important precedent for the semiconductor industry. To be sure, more than 95 percent of today’s web servers run on variants of the Linux operating system, while approximately 85 percent of smartphones sold worldwide use the open-source Android mobile operating system (OS). In addition, Red Hat recently became the first open source company to reach the $2 billion run-rate in annual sales.
Interested in learning more about RISC-V architecture? You can check out the official RISC-V Foundation site here.