Understanding Dennard scaling

This entry was posted on Thursday, August 4th, 2016.

In 1974, Robert H. Dennard co-authored a now-famous paper for the IEEE Journal of Solid State Circuits. Essentially, Dennard and his engineering colleagues observed that as transistors are reduced in size, their power density stays constant. Meaning, power use stays in proportion with area, as both voltage and current scale (downward) with length.

According to Prof. Dr.-Ing. Christian Märtin Hochschule of the Faculty of Computer Science at Augsburg University of Applied Sciences, power in CMOS chips can be modeled as dscaling. Q is the number of transistors, f the operating frequency of the chip, C the capacitance, V the operating voltage and I, the leakage current.


“With Dennard’s scaling rules the total chip power for a given area size stayed the same from process generation to process generation. At the same time, with a scaling factor of S √2, feature size [shrank] at a rate of 1/S (the scaling ratio), transistor count doubled (Moore’s Law) and the frequency increased by 40% every two years,” Hochschule explained. “With feature sizes below 65nm, these rules could no longer be sustained, because of the exponential growth of the leakage current.”

Indeed, says Hochschule, post-Dennard scaling leads to a power increase of s2per generation for the same die area. At the same time, utilization of a chip’s computing resources decreases with a rate offractionper generation.

“This means that a runtime large quantities of transistors on the chip have to be switched off completely, operated at lower frequencies, or organized in completely different or more energy efficient ways,” he continued. “For a given chip area energy efficiency can only be improved by 40% per generation. This dramatic effect, called dark silicon, already can be seen in current multicore process generations and will heavily affect future multicore and many-core processors.”

There is a general industry consensus that the laws of Dennard scaling broke down somewhere between 2005-2007. As Hochschule confirms, because threshold and operating voltage cannot be scaled any longer, it is no longer possible to keep the power envelope constant from generation to generation and simultaneously achieve potential performance improvements.

Nevertheless, Intel’s Mark Bohr remains bullish about the future of scaling in a post-Dennard world. In a 30 year retrospective on Dennard’s MOSFET scaling paper (published in 2014), he wrote:

“It is commonly recognized that following the simple scaling rules described by Dennard and his team back in 1974 is now no longer a sufficient strategy to meet future transistor density, performance and power requirements. But ours is a very inventive industry and new transistor technologies such as strained silicon, high- dielectrics, metal gates and multiple-gate devices have been or will be introduced to continue scaling. So although the letter of ‘Dennard’s Law’ can no longer be followed, it has gotten us very far over the past 30 years and the spirit is alive and well in transistor R&D facilities around the world.”