Part of a full suite of memory controller add-on cores, the AXI Interface Core is designed for use in applications requiring ARM’s Advanced eXtensible Interface (AXI). It requires the Read-Modify-Write core which is available separately.
Briefs
Memory Test Core Product Brief
Part of a full suite of memory controller add-on cores, the Memory Test Core provides comprehensive memory test support for chip and board verification. It can be used in conjunction with the Mem Test Analyzer Core to capture the actual and expected test data.
Reorder Core Product Brief
Part of a full suite of memory controller add-on cores, the Reorder Core reorders requests based first on priority and second on throughput optimization. Throughput optimization includes moving same bank/same row requests next to each other, same bank/different row requests away from each other, moving reads next to reads and writes next to writes.
ECC Core Product Brief
Part of a full suite of memory controller add-on cores, the Error Correction Coding (ECC) core implements the standard Hamming Code-based DRAM Single Error Correction (SEC) and Double Error Detection (DED) algorithms. The Read-Modify-Write core, offered separately, can be used in conjunction with the ECC Core when dealing with misaligned bursts.
PCIe 4.0 Controller Product Brief
The PLDA PCIe 4.0 Controller is designed to achieve maximum PCI Express (PCIe) 4.0 performance with great design flexibility and ease of integration. It comprises a complete SerDes subsystems with the Rambus PCIe 4.0 PHY or can integrate with PIPE 4.2-compliant 3rd-party PHYs. The controller is backwards compatible with PCIe 3.1/3.0.
MIPI Testbench Product Brief
The Northwest Logic MIPI Testbench emulates a MIPI device enabling end-to-end simulation of a MIPI design. It includes separate versions for CSI-2 Transmit, CSI-2 Receive, DSI-2 Host (Transmit), DSI-2 Peripheral (Receive), DSI Host, and DSI Peripheral.
