The Rambus PCIe 4.0 PHY with the PLDA PCIe 4.0 digital controller comprise a high-performance serial link subsystem. Optimized for power in challenging, high-loss channels, our PCIe 4.0 interface solution is ideal for performance-intensive data center, edge and graphics applications.
The PHY comes complete with a PMA hard macro that supports PCIe 4.0, 3.0, and 2.0 protocols and a physical coding sublayer (PCS) soft macro for PCIe that is PIPE 4.2 compliant. Integrated with the PLDA PCIe 4.0 digital controller, the PHY can also be paired with 3rd-party PIPE 4.2-compliant controllers.
The PHY has a minimal set of broadside control and are configurable in x2, x4 and x8 lane configurations. This gives the PHY improved flexibility and support for a wide range of applications. The PCIe 4.0 PHYs is rigorously tested through 3rd-party compliance testing and internal interoperability system testing.
In order to improve system margin and performance, our solution features transmit and receive equalization and full equalization adaptation. This ensures that data is recovered even in the presence of channel and system interference.
Our PCIe 4 SerDes PHY is available on TSMC, Global Foundry and Samsung process nodes.
Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation.
|Protocol||Signaling Rate (GT/s)||Application|
|PCIe 2.0||4||High bandwidth peripherals and graphics cards|
|PCIe 3.0||8||Enterprise solutions and chip to chip connectivity|
|PCIe 4.0||16||Hyperscale data center and big data applications|