Interface IP
PCIe 4.0 SerDes PHY
The Rambus PCI Express (PCIe) 4.0 SerDes PHY is designed to maximize interface speed in the difficult system environments found in high-performance computing. It is a low-power, area-optimized, silicon-proven IP designed with a system-oriented approach to maximize flexibility and ease integration for our customers. The PCIe 4 SerDes PHY supports PCIe 4.0, 3.0, and 2.0 and has full support for manufacturability.
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Product BriefHow Rambus PCIe 4.0 Works
The Rambus PCIe 4.0 SerDes PHY is a high-performance serial link subsystem. Optimized for power in challenging, high-loss channels, our PCIe 4.0 PHYs are ideal for networking, storage and data center systems.
The PHYs come complete with a PMA hard macro that supports PCIe 4.0, 3.0, and 2.0 protocols and a physical coding sublayer (PCS) soft macro for PCIe that is PIPE4.2 compliant.
PCIe 4.0 SerDes PHY Subsystem Example
They have a minimal set of broadside control and are configurable in x2, x4 and x8 lane configurations. This gives the PHYs improved flexibility and support for a wide range of applications. The PCIe 4.0 PHYs are rigorously tested through third party compliance testing and internal interoperability system testing.
In order to improve system margin and performance, our solution features transmit and receive equalization and full equalization adaptation. This ensures that data is recovered even in the presence of channel and system interference.
Our PCIe 4 SerDes PHYs are available on TSMC, Global Foundry and Samsung process nodes.
Solution Offerings
- Duplex lane configurations of x2, x4, and x8
- Flexible ASIC clocking
- Tight skew control of 2UI between lanes of the PMA
- 3-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
- Deterministic latency within +-1UI variation for Tx lane
- Continuous time linear equalizer (CTLE) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies
- Automatic calibration of key circuits to maximize performance and yields
- Support for bifurcation and quadfurcation modes
- 6-tap Rx DFE (decision feedback equalizer)
- Second-order CDR meeting SSC and RX sinusoidal jitter requirements
- Expandable register interface enabling communication with multiple PMAs and PCS-BIST soft macros
- Built-in Self Test (BIST) with ATPG and AC/DC boundary scan support
- Built-in PRBS pattern generation and checking for standalone loopback testing
- In-situ real-time monitoring and receive data eye schmoo
- Operation across a wide temperature range (-40 C to +125 C)
- Includes ESD structures
- SRIS support
- PMA Hard Macro
- Verilog models
- LEF abstracts (.lef)
- Timing models (.lib)
- CDL netlists (.cdl)
- ATPG models
- IBIS-AMI models
- GDSII layout
- DRC & LVS reports
- PCS-BIST Soft Macro
- RTL model
- Datasheet
- SoC Integration guide
- Optional design integration and bring-up support services
Comprehensive Chip and System Design Reviews
- Kickoff/Program Review
- Floor plan Review
- Test/Characterization Plan Review
- Package Design Review
- Board Design Review
- Final Chip Integration Review
- Bring-up and Test Review
Engineering Design Services:
- Package design
- System board layout
- Statistically-based signal and power integrity analysis
Protocol Compatibility
| Protocol | Data Rate (Gbps) | Application |
|---|---|---|
| PCIe 2.0 | 4 | High bandwidth peripherals and graphics cards |
| PCIe 3.0 | 8 | Enterprise solutions and chip to chip connectivity |
| PCIe 4.0 | 16 | Hyperscale data center and big data applications |
SerDes Signal Integrity Challenges at 28Gbps and Beyond
Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation. For PAM4 signals, the baud rate equals one-half the bit rate and the Nyquist frequency equals one-fourth the bit rate. Compared to PAM2/NRZ, PAM4 cuts the bandwidth for a given data rate in half by transmitting two bits in each symbol. This allows engineers to double the bit rate in the channel without doubling the required bandwidth.
Inventions
Phase Interpolator-Based CDR
Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.
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