The Rambus PCI Express (PCIe) 4.0 SerDes PHY is designed to maximize interface speed in the difficult system environments found in high-performance computing. It is a low-power, area-optimized, silicon-proven IP designed with a system-oriented approach to maximize flexibility and ease integration for our customers. The PCIe 4 SerDes PHY supports PCIe 4.0, 3.0, and 2.0 and has full support for manufacturability.
The Rambus PCIe 4.0 SerDes PHY is a high-performance serial link subsystem. Optimized for power in challenging, high-loss channels, our PCIe 4.0 PHYs are ideal for networking, storage and data center systems.
The PHYs come complete with a PMA hard macro that supports PCIe 4.0, 3.0, and 2.0 protocols and a physical coding sublayer (PCS) soft macro for PCIe that is PIPE4.2 compliant.
PCIe 4.0 SerDes PHY Subsystem Example
They have a minimal set of broadside control and are configurable in x2, x4 and x8 lane configurations. This gives the PHYs improved flexibility and support for a wide range of applications. The PCIe 4.0 PHYs are rigorously tested through third party compliance testing and internal interoperability system testing.
In order to improve system margin and performance, our solution features transmit and receive equalization and full equalization adaptation. This ensures that data is recovered even in the presence of channel and system interference.
Our PCIe 4 SerDes PHYs are available on TSMC, Global Foundry and Samsung process nodes.
Comprehensive Chip and System Design Reviews
Engineering Design Services:
|Protocol||Data Rate (Gbps)||Application|
|PCIe 2.0||4||High bandwidth peripherals and graphics cards|
|PCIe 3.0||8||Enterprise solutions and chip to chip connectivity|
|PCIe 4.0||16||Hyperscale data center and big data applications|
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