Addressing the growing demand for readily available solutions that implement Differential Power Analysis (DPA) countermeasures, Rambus Cryptography Research developed a family of semiconductor IP cryptographic cores and software libraries that are designed to protect against side-channel attack vulnerabilities. Learn more about our DPA Resistant Software Libraries, and its flexible integration with standard cipher modes such as Cipher Block Chaining (CBC), Electronic Code Book (ECB), etc. in this brief.
Briefs
DPA Resistant Hardware Cores Product Brief
Rambus DPA Resistant Hardware Cores, when integrated into an SoC, prevent against the leakage of secret cryptographic key material through attacks. These superior performance cores are easy to integrate into SoCs and FPGAs, providing robust side-channel resistance across different security and performance levels. Our DPA Resistant Hardware Cores support industry standard cryptographic algorithms and random number generators such as: AES, TDES, SHA-2, HMAC, RSA and ECC across multiple operating modes.
On-Chip Noise Monitor Product Brief
Our On-Chip Power Supply Noise Monitor has been developed to overcome the characterization challenges of low-power, high-performance interfaces and electronic systems. It is a compact IP block embedded on-chip and works in conjunction with our LabStation™ Validation Platform to enable noise measurements directly on the chip.
LabStation Validation Platform Product Brief
Design complexity for advanced SoCs rises with each new process node, performance increase, and addition of new IP blocks. Designers are faced with increasing challenges to confidently verify and validate functionality of their chips. The LabStation Validation platform is a comprehensive tool suite for the rapid bring-up, validation and characterization of complex low-power, high-performance memory and serial link IP. It is designed to be easy to use and improve productivity while providing improved accuracy of test results and confidence is system performance.
LPDDR3 DRAM Product Brief
LPDDR3 PHY Product Brief
Fully compliant with LPDDR3 and LPDDR2 DRAM specifications, our LPDDR3 PHY pairs with the LPDDR3 DRAM to create a memory subsystem that supports data rates of up to 2133 Mbps, and reduces active memory system power by up to 25% and active DRAM power by up to 30%. This enables a significantly improved thermal profile and an increased battery life in the end device. The improved thermal profile also enables the memory system to run at peak bandwidth for longer periods of time, which translates to better overall performance in the end systems.
The improvement in power consumption is a result of Low Voltage Swing Terminated Logic (LVSTL), a single-ended, ground-terminated signaling technology, used while in R+ mode. LVSTL features a significantly reduced signal swing versus the 1.2 volt HSUL (High Speed Unterminated Logic) signal swing of standard LPDDR3. Reduced signal swing translates to significantly reduced IO power at high data rate, which is a major component of DRAM power. By supporting LVSTL and HSUL signaling, LPDDR3 offers a low-power mode while maintaining compatibility with LPDDR3 and LPDDR2 DRAM standards.