First Demonstration of Rambus’ R+ Enhanced Industry Standards Platform and 3D IC Interposers Technology
SANTA CLARA, CALIFORNIA, UNITED STATES – 01/29/2013
|Rambus Inc. (NASDAQ: RMBS)
Santa Clara Convention Center
Santa Clara, CA
|January 28–31, 2013
At DesignCon 2013, Rambus engineers and scientists will present six technical papers on topics such as: mixed signal designs, 3D interposer design, memory controllers and 3D DRAM, high-speed coded differential signaling, and high-speed parallel buses.
Additionally, Rambus will be demonstrating various innovations in its booth (#301), including: R+ technologies for extending main memory beyond DDR4, R+ DDR3 memory interface solution, R+ DDR3/GDDR5 multi-modal interface technology, and 3D IC memory technology from Rambus Labs. For additional details, visit www.rambus.com.
Tuesday, January 29, 2013
Title: A Reusable Generic Platform for Validation and Characterization of High-Speed Mixed Signal Designs
8:30 a.m.–9:10 a.m. – Ballroom DPresenter: Dr. Chuck Yuan, Director of Engineering, Rambus Inc.
Sanku Mukherjee, Narayanan Mayandi, Brian Tsang, Sreeja Menon, Norman Chan and Arul Sendhil, Rambus Inc.
Rambus scientists and engineers will share innovations around a reusable test chip architecture, a generic package and a generic PCB infrastructure for fast validation of mixed signal IP.
Title: Enabling DFT Logic and Timing Verification in Mixed-Signal Designs
2:50 p.m.-3:30 p.m. – Ballroom B
Bing Chuang and Kaneez Tumpa, Rambus Inc.
In this talk, Rambus will discuss a design-for-test (DFT) methodology for getting test coverage in custom digital data paths used in the design of high-speed interfaces.
Wednesday, January 30, 2013
Title: 3D Si Interposer Design and Electrical Performance Study
9:20 a.m.-10:00 a.m. – Ballroom B
Mandy (Ying) Ji, Ming Li, Julia Cline, David Secker and Kevin Cai, Rambus Inc.
This session provides design guidelines for signal routing and signal integrity (loss, impedance control, crosstalk, eye diagram, etc.) for frequencies up to 20 GHz. Power delivery guidelines will be presented for RDL layers, taking into consideration the IR drop challenges.
Title: A 256-GB/s Memory Subsystem Built Using a Double-Sided IC Package with a Memory Controller and 3D-Stacked DRAM
10:15 a.m.-10:55 a.m. – Ballroom C
Scott Best, David Secker, Thomas Giovannini, Don Mullen, Ming Li and Mandy Ji, Rambus Inc.
In this session, Rambus will present a processor and DRAM memory subsystem built using a double-sided, flip-chip substrate with a processor die on one side of the package and a thermally isolated, disaggregated memory chip on the other side.
Title: Design and Analysis of a Twisted Line Structure for High Speed Coded Differential Signaling
10:15 a.m.-10:55 a.m. – Ballroom D
Wendem Beyene, Rambus Inc.
This session introduces the design and analysis of a high-speed parallel interface for a new signaling scheme called coded differential (CD) signaling.
Title: Accurate Receiver Clock Positioning in High-Speed Parallel Buses
11:05 a.m.-11:45 a.m. – Ballroom C
Arun Vaidyanath, Christopher Madden and Yohan Frans, Rambus Inc.
This session reviews the pros and cons of various approaches to center the receiver clock. Even with accurate positioning of the receiver clock, the system will still experience drift due to thermal and other effects. This session also presents an efficient way to periodically calibrate the timing center to mitigate timing drift due to temperature variation.
About Rambus Inc.
Rambus is the innovative technology solutions company that brings invention to market. Unleashing the intellectual power of our world-class engineers and scientists in a collaborative and synergistic way, Rambus invents, licenses and develops solutions that challenge and enable our customers to create the future. While best known for creating unsurpassed semiconductor memory architectures, Rambus is also developing world-changing products and services in security, advanced LED lighting and displays, and immersive mobile media. Additional information is available at www.rambus.com.