On March 2, Rambus, along with partners MLove and IXDS, will be hosting 4YFN’s “Eyes of the IoT” workshop and reception from 2:00 p.m. – 6:00 p.m. “The Internet of Things (IoT) depends on data and smart sensors are essential to effectively capturing that data,” explained Kendra De Berti, a director at Rambus.
Rambus to host “Eyes of the IoT” workshop at MWC 2015
CryptoFirewall ASIC security cores integrated into 65 chipsets
Designed by the Rambus Cryptography Research Division (CRD), self-contained CryptoFirewall™ (CF) ASIC cores offer a secure hardware-based root-of-trust for content protection applications. According to Cynthia Yu, a Rambus CRD director, CryptoFirewall ASIC security cores have been integrated into at least 65 chipsets, including those manufactured by Ali, ST, MStar, Broadcom, Entropic and ViXS.
iRunway report highlights seminal Rambus patents
A recent iRunway report on the semiconductor memory landscape ranked Rambus in the fourth position of the top ten seminal patent holders in DRAM technology.
Jerome Nadel to talk smart cities @ MWC 2015
On March 3rd, Rambus CMO Jerome Nadel will participate in 4YFN’s MWC 2015 panel discussion about the Internet of Things (IoT), smart sensors and the evolution of smart cities.
Mobile DRAM industry valued at over $3.6 billion
DRAMeXchange, a division of TrendForce, recently confirmed worldwide mobile DRAM revenue of US$3.607 billion in the fourth quarter of 2014 – representing 27.8% of DRAM industry value and a 4.2% quarterly increase. In addition, mobile DRAM made up nearly 40% of all DRAM shipments.
From GDDR to HBM
A recent KitGuru report suggests AMD has designed its upcoming Radeon R9 380X with high bandwidth memory, or HBM, a next-gen stacked DRAM memory standard. “Although HBM provides DDR3 – like bit rate per pin (HBM1=1GHz, HBM2=2GHz), the standard more than compensates with its channel of 128 bits each,” Loren Shalinsky, a Strategic Development Director at Rambus, explained. “This results in an interface that can support 1024 bits x 2GHz = 2048 Gbits/sec (256GB/sec). The HBM stack (as defined in HBM2) can actually have up to 8 die in the stack. The standard doesn’t specify how many channels are on each die.”
