5G represents a revolution in mobile technology with performance that will rival that of wireline networks. 5G’s Ultra-reliable Low Latency Communication (uRLLC) links will enable a profusion of artificial intelligence (AI)-powered IoT devices from delivery drones to smart cities. The rapid rise in the number of smart IoT devices, coupled with expanded connectivity, will greatly escalate the growth of data and network traffic.
5G and AI Raise Security Risks for IoT Devices
Dangers of Counterfeit Semi Chips
In 2019, the worldwide fake semi market was estimated at $75 billion according to Industry Week. This counterfeit chip market particularly prevalent in the government and defense industries. According to a US government report, more than 1 million counterfeit electronic components were used in 1,800 instances affecting military aircraft and missiles.
Rambus’ HBM2E Memory Controller & PHY Offer Chipmakers Cost-Effective Designs
The latest generation of high-bandwidth memory, HBM2E, is around the corner. Now that Samsung has started mass production of its HBM2E memory stacks, Rambus has unveiled its controller and PHY (physical interface) designs.
Rambus Develops HBM2E Controller & PHY: 3.2 Gbps, 1024-Bit Bus
The latest enhancements to the HBM2 standard will clearly be appreciated by developers of memory bandwidth-hungry ASICs, however in order to add support of HBM2E to their designs, they are also going to need an appropriate controller as well as physical interface. For many companies developing of such IP in-house does not make financial sense, so Rambus has designed a highly-integrated HBM2E solution for licensing.
2.5D/3D Packaging Solutions for AI and HPC
For AI and HPC applications, HBM2E memory can deliver excellent bandwidth, capacity and latency in a very compact footprint thanks to its 2.5D/3D structure. The flipside is that this same structure leads to greater design complexity and raises a new set of implementation considerations.
Memory For Advanced Designs
The 2020 Designcon conference included many talks and exhibits with a storage and memory focus. Both Rambus and Teledyne LeCroy had tutorials on design and connectivity for leading edge electronic components and systems as well as testing memory systems. This piece will look at some material from the tutorials and exhibits that can inform us about disaggregated processing developments, high speed chip to chip interfaces and memory for AI applications.
