Vehicle systems and the semiconductors used within them are some of the most complex electronics seen today. In the past, electronics going into vehicle systems implemented flat architectures with isolated functions controlling various components of the power train and vehicle dynamics. However, to support the realization of Level 4 and Level 5 (L4/L5) autonomous driving, a massive restructure is underway. The software-defined vehicle, the automotive Ethernet, vehicle-to-everything (V2X) connectivity, and domain controller units are just some of the new technologies required to realize L4/L5 capabilities. Ensuring all these new systems are both functionally safe and secure from cyberattacks is mission critical.
The growth of computing, graphics, neural processing power, communication bandwidth, and storage capacities have enabled amazing solutions. These innovations have created great value for society, and that value must be protected from exploitation by adversaries. This whitepaper explores many of these major technology changes and how Rambus’ security offerings help in tackling the new embedded security challenges of device and silicon manufacturers.
PUFs are mixed-signal circuits which rely on variations unique to a specific chip to self-generate a digital “fingerprint.” Most PUFs require a “helper-data” image that is generated during the initial digitization process, also known as Enrollment. Leveraging the chip-unique transformation function of PUFs and encrypted helper data, an unclonable challenge-response mechanism can be implemented that can distinguish authentic chips from perfect adversarial clones.
AI/ML is increasingly pervasive across all industries driven by a massive wave of digitization. Data, the raw material of AI/ML and Deep Learning algorithms, is available in enormous quantities from all aspects of business operations. AI/ML promises great gains in responsiveness and adaptability in an ever-changing technology landscape, and industries are enthusiastically responding to that appeal. Concurrently, the vast value creation of AI/ML make it an inviting target for adversaries who aim to compromise or steal. Learn about the attack vectors against AI/ML and solutions for safeguarding its assets.
Building security in an SoC aiming to meet the goals set by the ARM Platform Security Architecture (PSA) is a complex matter. This is compounded by the complexity of modern-day SoCs comprising multiple processors, security domains and security levels. The Rambus root of trust provides a solid foundation for the SoC security architecture ticking ‘all the boxes’ for reaching the security goals, while offering extensive support for effective integration into a complex TrustZone-based SoC infrastructure.
Built around a custom RISC-V CPU, the Rambus CryptoManager Root of Trust (CMRT) is at the forefront of a new category of programmable hardware-based security cores. Siloed from the primary processor, it is designed to securely run sensitive code, processes and algorithms. More specifically, the CMRT provides the primary processor with a full suite of security services, such as secure boot and runtime integrity, remote attestation and broad crypto acceleration for symmetric and asymmetric algorithms.