At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Download The Impact of Higher Data Rate Requirements on MIPI CSI and MIPI DSI Designs to learn how MIPI Alliance Camera Serial Interface and Display Serial Interface standards are evolving to meet the needs for higher data rate interfaces.
To learn more about the our MIPI offerings, click here.
Steven Woo, VP of Systems and Solutions, presents about the shifting performance bottlenecks driving future silicon design at DesignCon 2016.
Moore’s Law has relentlessly delivered tremendous improvements in processing performance and functionality for several decades, enabling newer generations of processors to surpass the capabilities of their predecessors. While processors will continue to become more feature-rich, the emergence of new computing paradigms and slower rates on improvement in other areas mean that power and performance bottlenecks moving away from processors into others subsystems. Moving data between processing elements, memory, storage, and across networks is becoming a growing challenge, and concerns about power and security are forcing chip and system architects to rethink not only how silicon needs to be architected, but systems as a whole. In this talk I’ll discuss how these concerns are driving changes in the way we think about both silicon and systems in the future.
To download the presentation, please fill out the form below.
