With the new era of every device getting smart and data getting bigger, there has been a constant increase in bandwidth and speed requirements for networking communications on the back end side. From the age of chips communicating at 1Gbps to 10Gbps to 40Gbps to 100Gbps and setting the stage for 400Gbps and 1Tbps in coming years, everyone wants to communicate faster and faster but at the same time by being more efficient (energy consumption) and smaller (silicon area). With the new technology nodes trending in even faster than Moore’s law, there are variety of dimensions and tradeoffs which are required to define a Serial link for the next generation needs to make a particular solution effective on all fronts.
Steven Woo, VP of Systems and Solutions, presents about the shifting performance bottlenecks driving future silicon design at DesignCon 2016.
Moore’s Law has relentlessly delivered tremendous improvements in processing performance and functionality for several decades, enabling newer generations of processors to surpass the capabilities of their predecessors. While processors will continue to become more feature-rich, the emergence of new computing paradigms and slower rates on improvement in other areas mean that power and performance bottlenecks moving away from processors into others subsystems. Moving data between processing elements, memory, storage, and across networks is becoming a growing challenge, and concerns about power and security are forcing chip and system architects to rethink not only how silicon needs to be architected, but systems as a whole. In this talk I’ll discuss how these concerns are driving changes in the way we think about both silicon and systems in the future.
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