With the publishing of the HBM3 update to the High Bandwidth Memory (HBM) standard, a new king of bandwidth is crowned. The torrid performance demands of advanced workloads, with AI/ML training leading the pack, drive the need for ever faster delivery of bits. Memory bandwidth is a critical enabler of computing performance, thus the need for the accelerated evolution of the standard with HBM3 representing the new benchmark.
Interface IP
Avery Design Systems and Rambus Extend Memory Model and PCIe® VIP Collaboration
Tewksbury, MA. and San Jose, Calif. – May 19, 2021 – Avery Design Systems, a leader in functional verification solutions, and Rambus Inc. (NASDAQ: RMBS), a provider of industry-leading chips and silicon IP making data faster and safer, announced today they are extending their long-term memory model and PCIe® Verification IP (VIP) collaboration.
Rambus utilizes Avery’s high-quality, full-featured memory models to verify their memory controllers including HBM2/2E, GDDR6, LPDDR4, and DDR3/4. Rambus includes these memory models in its customer deliveries to enable out-of-the-box simulations with the delivered IP. Customers can then license the Avery memory models for use in full SoC verification. Rambus utilizes Avery’s PCIe VIP to verify its PCIe 5.0/4.0 controllers, including Endpoint, Root Port and Retimer modes, and PHYs.
“Avery’s cutting-edge VIP has enabled Rambus to verify controllers which support the most advanced features needed by customers in their current and next-generation designs,” said Brian Daellenbach, senior director of Digital Controllers, IP Cores at Rambus. “The collaboration between Avery and Rambus has helped both companies offer fully-verified IP solutions addressing the latest market requirements.”
“Rambus and Avery are both focused on creating best-in-class, robust, pre-validated memory and PCIe IP solutions which streamline the design and verification process for our customers. We look forward to continuing our collaboration to address the current and next-generation protocols being used by the market,” said Chris Browy, vice president sales/marketing of Avery.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
Compute Express Link and CXL are trademarks of the CXL Consortium
PCI Express and PCIe® are trademarks of PCI-SIG
AI Drives Memory Interconnect Evolution
TORONTO — Location, location, location is not a mantra limited to real estate. To meet the needs of artificial intelligence (AI) and machine learning applications, it increasingly applies to where data needs to reside, and the memory that stores it.
4Gbps!HBM2E内存接口再现性能标杆
人工智能/机器学习(AI/ML)在全球范围内的迅速兴起,正推动着制造业、交通、医疗、教育和金融等各个领域的惊人发展。从2012年到2019年,人工智能训练能力增长了30万倍,平均每3.43个月翻一番,就是最有力的证明。支持这一发展速度需要的远不止摩尔定律,人工智能计算机硬件和软件的各个方面都需要不断的快速改进。
Impact of AI on Data Center Infrastructure
The 3rd AI Hardware Summit took place virtually earlier this month and it was exciting to see how quickly the ecosystem has evolved and to learn of the challenges the industry has to solve in scaling artificial intelligence (AI) infrastructure. I would like to share highlights of the Summit, along with other notable observations from the industry in the area of accelerated computing.
5G Network Infrastructure to Drive Memory Diversity
For consumers, 5G brings with it the potential of a better user experience on smartphones, but its influence on memory uptake won’t be at the device level.
Handset makers will continue to add more DRAM and flash storage to smartphones regardless of network connections. The memory in 5G network infrastructure will be even more diverse given the many use cases for the next generation of mobile networking.