- Provides critical building block to deliver data for next-generation data center, networking, high-performance computing (HPC), artificial intelligence (AI) and machine learning (ML) applications
- Delivers superior power, performance and area (PPA) for extra short reach (XSR) links with innovative architecture designed for leading-edge 7nm process node
- Expands SerDes PHY portfolio for 112G OIF-CEI industry standard
SUNNYVALE, Calif. – Sep. 25, 2019 – Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced the tapeout of its 112G XSR SerDes PHY on a leading-edge 7nm process node optimized for PPA to support data center, networking, HPC, AI and ML applications. As the industry continues to adopt chiplet architectures for networking and compute applications, the Rambus 112G XSR SerDes PHY represents the latest advancement in high-speed signaling technology for die-to-die (D2D) and die-to-optical engine (D2OE) connections. Rambus continues at the forefront of implementing 112G designs to address the needs for next-generation data-intensive applications.
In today’s increasingly connected world, zettabytes of data are generated constantly by a wide range of devices including IoT endpoints such as vehicles, wearables, smartphones and appliances. AI and ML add new workloads and new data streams from the data center to the edge, driving new architectures to move data. These new architectures, combined with the trend toward chip disaggregation and the industry’s transition to 400Gb and 800Gb Ethernet, will require new, faster interconnect solutions.
“As semiconductor markets turn towards chiplets to enable their high-performance products, chip-to-chip interconnects will be critical for maintaining high speed and signal integrity across variable physical distances,” said Shane Rau, research vice president, computing semiconductors at IDC. “SerDes PHYs at advanced process nodes, like the 7nm 112G XSR, enable that speed and signal integrity.”
“Our 112G XSR SerDes PHY is implemented in the leading-edge 7nm process technology, providing chip and system architects the most advanced platform for their designs,” said Hemant Dhulla, vice president and general manager of IP cores at Rambus. “We are excited to continue our tradition of delivering leading-edge IP solutions that address the systems design challenges of the most demanding applications in networking, HPC and AI.”
The Rambus 112G XSR SerDes PHY will deliver enterprise-class performance within D2D and D2OE interconnects for 400Gb and 800Gb Ethernet environments. To achieve the demanding data rates of these high-speed applications requires an innovative SerDes architectural approach.
The Rambus 112G XSR SerDes PHY includes:
- High-bandwidth connectivity greater than 800 Gbps per millimeter of beachfront making it ideal for D2D and D2OE interconnects in networking and HPC applications
- Designed to provide a low-power, high-speed interface that supports chip disaggregation
- Best-in-class architecture for power, performance, area (PPA) with approximately 1 pJ/bit or 1mW/Gbps power
- Compliance with Optical Internetworking Forum Common Electrical I/O Consortium (OIF-CEI) standard
Availability and Additional Information
The Rambus 112G XSR SerDes PHY is the latest addition to the Rambus leading-edge portfolio of SerDes solutions including the 112G LR SerDes PHY announced earlier this year. The PHY is available for licensing, and early access design customers can engage today. To learn more about Rambus SerDes technology, visit Rambus Booth #408 at the TSMC 2019 Open Innovation Platform® Ecosystem Forum on September 26, 2019 at the Santa Clara Convention Center in Santa Clara, CA.
For more information on various Rambus SerDes PHY offerings, please visit rambus.com/serdes.