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From 4G to 5G The current 4G cellular networks that drive our computers, tablets and smartphones are poised for a major upgrade as we approach 5G. To understand where we’re going with 5G, we need to know where we’ve been. In the 1990s, cellular and data networks had anemic connection speeds and computing power, at […]
HBM2 PHY We are showcasing our HBM2 PHY at the GLOBALFOUNDRIES Technology Conference at the Hyatt Regency Santa Clara (table #6). Designed for systems that require low latency and high bandwidth memory, our HBM2 PHY is built on GLOBALFOUNDRIES advanced 14nm Power Plus (LPP) process technology. The PHY is fully compliant with the JEDEC HBM2 […]
The Rambus DDR5 Server DIMM buffer chipset is the industry’s first functional silicon targeted for next-generation DDR5. Our chips are designed to enable high-capacity, high-speed and robust memory solutions for tomorrow’s most demanding enterprise and data center applications.
Juniper Research analysts are forecasting 1.4 billion 5G connections by 2025, an increase from just 1 million – upon commercial launch of 5th generation wireless systems – in 2019. Unsurprisingly, the U.S. alone is expected to account for over 30% of global 5G IoT connections by 2025, with the highest number of 5G connections for […]
Juniper Research analysts forecast that wireless VR headsets (smartphone-based and standalone) data consumption will increase by over 650% over the next 4 years, from nearly 2,800PB (Petabytes) in 2017 to over 21,000PB in 2021. Moreover, when combined with traffic generated by VR headsets tethered to PCs and consoles, data consumption is expected to reach over […]
There are many who would dispute the notion that we are living in a post-GIGO (Garbage In, Garbage Out) world. Nevertheless, it is undeniable that the ubiquitous Internet of Things (IoT) has created a digital tsunami of valuable data generated by a wide range of devices, systems and IoT endpoints such as vehicles, wearables, smartphones […]
The Rambus NVRCD is the industry’s 1st JEDEC-standard persistent memory register clock driver (NVRCD) in full production for use with NVDIMM-N and emerging NVDIMM-P solutions.
Rambus is attending the Samsung Foundry Forum at the Santa Clara Marriott on May 24th. The company will be showcasing its 56G SerDes PHY, which is being developed on Samsung’s 10nm LPP (Low-Power Plus) process technology. As we’ve previously discussed on Rambus Press, our 56G SerDes PHY supports PAM-4 and NRZ signaling and data rates from […]
Gary Hilson of the EE Times has written a detailed article about Rambus’ 56G SerDes PHY. As Hilson notes, the analog-to-digital converter (ADC) and (DSP) architecture of Rambus’ 56G SerDes PHY is designed meet the long-reach backplane requirements for the industry transition to 400 GB Ethernet applications. This means it can support scaling to speeds […]
Rambus VP of Systems and Solutions Steven Woo recently penned an article for ChipEstimate about the changing data center. According to Woo, the evolution of computing from the PC-centric world of the 1980’s-1990’s to today’s mobile+cloud environment has been a primary driver for change in processors, memory, storage and networks. Clock speeds and the breakdown […]