At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Found 220 Results
SK hynix launches first DDR5 DRAM
https://www.newelectronics.co.uk/electronics-news/sk-hynix-launches-first-ddr5-dram/230998/#new_tabSK hynix has announced the launch of the world’s first DDR5 DRAM, optimised for Big Data, Artificial Intelligence (AI), and machine learning (ML) as a next generation standard of DRAM.
World’s first DDR5 DRAM module has focus on power
https://www.eenewspower.com/news/worlds-first-ddr5-dram-module-has-focus-power#new_tabSK hynix is launching the world’s first DDR5 memory module, aimed at Big Data, Artificial Intelligence (AI), and machine learning (ML) with a key focus on power consumption. The DDR5 memory module is supports transfer rate of 4.8 to 5.6Gbit/s, 1.8 times faster than the previous generation, at 1.1V rather than 1.2V. This reduces the […]
Rambus Advances HBM2E Performance to 4.0 Gbps for AI/ML Training Applications
https://www.rambus.com/rambus-advances-hbm2e-performance-to-4-0-gbps-for-ai-ml-training-applications/Highlights: Fully-integrated HBM2E memory interface solution, consisting of verified PHY and controller, achieves industry’s fastest performance New benchmark in performance supports accelerators requiring terabyte-scale bandwidth for artificial intelligence/machine learning (AI/ML) training applications Partners with SK hynix and Alchip to develop 2.5D HBM2E memory system solution using TSMC N7 process and CoWoS® advanced packaging technologies Offers unrivaled […]
Rambus Delivers 112G XSR/USR PHY on TSMC 7nm Process for Chiplets and Co-Packaged Optics in Networking and Data Center
https://www.rambus.com/112g-xsr-usr-phy-on-tsmc-7nm-process-for-chiplets-and-co-packaged-optics-in-networking-and-data-center/Highlights: Expands comprehensive portfolio of cutting-edge IP designed on TSMC’s industry-leading 7nm (N7) process Enables the most power- and cost-efficient solution for die-to-die (D2D) and die-to-optical engine (D2OE) connectivity over Extra Short Reach (XSR) and Ultra Short Reach (USR) channels Accelerates next-generation data center, networking, 5G, high-performance computing (HPC), and artificial intelligence/machine learning (AI/ML) applications […]
Side-Channel Attacks Target Machine Learning (ML) Models
https://www.rambus.com/blogs/side-channel-attacks-target-machine-learning-ml-models/Written by Paul Karazuba for Rambus Press A team of North Carolina State University researchers recently published a paper that highlights the vulnerability of machine learning (ML) models to side-channel attacks. Specifically, the team used power-based side-channel attacks to extract the secret weights of a Binarized Neural Network (BNN) in a highly-parallelized hardware implementation. “Physical […]
Hardware Security for AI Accelerators
https://go.rambus.com/hardware-security-for-ai-accelerators#new_tabDedicated accelerator hardware for artificial intelligence and machine learning (AI/ML) algorithms are increasingly prevalent in data centers and endpoint devices. These accelerators handle valuable data and models, and face a growing threat landscape putting AI/ML assets at risk. Using fundamental cryptographic security techniques performed by a hardware root of trust can safeguard these assets from […]
High-Performance Memory for AI/ML and HPC: Part 2
https://www.rambus.com/blogs/high-performance-memory-for-ai-ml-and-hpc-part-2/In part one of this two-part series, Semiconductor Engineering Editor in Chief Ed Sperling and Rambus Sr. Director of Product Management Frank Ferro took a closer look at the various types of memory that system designers are using to support artificial intelligence (AI), machine learning (ML), and high-performance computing (HPC) applications. In this blog post, […]
High-Performance Memory for AI/ML and HPC: Part 1
https://www.rambus.com/blogs/high-performance-memory-for-ai-ml-and-hpc-part-1/Semiconductor Engineering Editor in Chief Ed Sperling recently spoke with Rambus Sr. Director of Product Management Frank Ferro about designing high-performance memory subsystems for artificial intelligence (AI), machine learning (ML), and high-performance computing (HPC) applications. As Ferro notes, there is plenty of compute (CPU) power available today to support the above-mentioned markets. “[However], the advances […]
Rambus Announces Complete 800G MACsec Solution for Enhanced Data Center and 5G Infrastructure Security
https://www.rambus.com/rambus-announces-complete-800g-macsec-solution-for-enhanced-data-center-and-5g-infrastructure-security/Highlights: Integrated hardware-based solution delivers full line-rate MACsec security at 100G to 800G data rates Supports multi-channel, multi-rate implementations with flexible bandwidth allocation Delivers enhanced data security for cloud, enterprise and carrier network applications as well as network-attached, high-performance computing (HPC) and AI/ML SUNNYVALE, Calif. – Apr. 29, 2020 – Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and […]
Memory Systems for AI: Part 4
https://www.rambus.com/blogs/memory-systems-for-ai-part-4/Written by Steven Woo for Rambus Press In part three of this series, we discussed how a Roofline model can help system designers better understand if the performance of applications running on specific processors is limited more by compute resources, or by memory bandwidth. Rooflines are particularly useful when analyzing machine learning applications like neural […]
