Found 285 Results

Rambus CXL IP: A Journey from Spec to Compliance

Driven by our unwavering commitment to quality and performance, a Rambus team of engineers, validation experts, and architects have been taking part in CXL® Compliance Test Events to ensure the flawless performance and market readiness of our CXL Controller IP. We are pleased to report that our CXL 2.0 Controller IP has gained compliance in […]

New CXL 3.1 Controller IP for Next-Generation Data Centers

The AI boom is giving rise to profound changes in the data center; compute-intensive workloads are driving an unprecedented demand for low latency, high-bandwidth connectivity between CPUs, accelerators and storage. The Compute Express Link® (CXL®) interconnect offers new ways for data centers to enhance performance and efficiency. As data centers grapple with increasingly complex AI […]

Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.1

The PCI Express® (PCIe®) interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the torrid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.1 jumps signaling to 64 GT/s with some of the […]

Compute Express Link (CXL): All you need to know

[Last updated on: January 23, 2024] In this blog post, we take an in-depth look at Compute Express Link®™ (CXL®™), an open standard cache-coherent interconnect between processors and accelerators, smart NICs, and memory devices. We explore how CXL can help data centers more efficiently handle the tremendous memory performance demands of generative AI and other advanced workloads. […]

Post-quantum Cryptography (PQC): New Algorithms for a New Era

[Updated December 7th, 2023] Post-Quantum Cryptography (PQC), also known as Quantum Safe Cryptography (QSC), refers to cryptographic algorithms designed to withstand attacks by quantum computers. Quantum computers will eventually become powerful enough to break public key-based cryptography, also known as asymmetric cryptography. Public key-based cryptography is used to protect everything from your online communications to […]

QSE-IP-86 Quantum Safe Engine Product Brief

The Rambus Quantum Safe Engine (QSE) IP provides Quantum Safe Cryptography acceleration for ASIC, SoC and FPGA devices. The QSE supports the FIPS 203 ML-KEM and FIPS 204 ML-DSA draft standards. Download the product brief to find out about the QSE features, learn how the QSE can be used for multiple use cases, and review […]

QSE-IP-86 Quantum Safe Engine

QSE-IP-86 Quantum Safe Engine With Quantum Safe Cryptography Contact Us The Rambus Quantum Safe Engine (QSE) IP provides Quantum Safe Cryptography acceleration for ASIC, SoC and FPGA devices. The QSE-IP-86 core is typically integrated in a hardware Root of Trust or embedded secure element in chip designs together with a PKE-IP-85 core that accelerates classic public […]

Quantum Safe Cryptography IP

Quantum Safe Cryptography IP Protection against quantum computer attacks using NIST and CNSA algorithms Contact Us Quantum computers will be able to rapidly break current asymmetric encryption, placing important data and assets at risk. Rambus Quantum Safe IP solutions offer a hardware-level security solution to protect data and hardware against quantum computer attacks using NIST […]

Rambus Protects Data Center Infrastructure with Quantum Safe Engine IP

Highlights: Expands industry-leading family of Quantum Safe IP solutions for data center and government hardware security Integrates into root of trust or embedded secure element in advanced SoCs and FPGAs Delivers cryptographic acceleration with leading NIST-selected quantum-resistant algorithms SAN JOSE, Calif. – December 4, 2023 – Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon […]

CXL 3.0 Controller

CXL 3.1 Controller Contact Us The Rambus Compute Express Link® (CXL®) 3.1 Controller is a parameterizable design for ASIC and FPGA implementations. It leverages the Rambus PCIe 6.1 Controller architecture for the protocol and adds the CXL.cache and CXL.mem protocols specific to CXL. The controller exposes a native Tx/Rx user interface for traffic […]

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