Home > Search
Found 301 Results
[Updated April 14, 2025] Post-Quantum Cryptography (PQC), also known as Quantum Safe Cryptography (QSC), refers to cryptographic algorithms designed to withstand attacks by quantum computers. Quantum computers will eventually become powerful enough to break public key-based cryptography, also known as asymmetric cryptography. Public key-based cryptography is used to protect everything from your online communications to […]
[Last updated on April 8, 2025] A root of trust is the security foundation for an SoC, other semiconductor device or electronic system. However, its meaning differs depending on who you ask. From our perspective, the hardware root of trust contains the keys for cryptographic functions and is usually a part of the secure boot […]
[Updated April 7, 2025] With the ongoing efforts of the Rambus engineering team, we have now achieved compliance to CXL 2.0 with our CXL Controller IP, and it has been added to the Integrators List. Company Name Product Name Device ID Device Type Feature Set Spec Revision PHY Speed Max Lane Form Factor Function Compliance […]
CryptoManager Hub (CH-7xx) and CryptoManager Core (CC-7xx) ISO 21434 Automotive-grade Foundational Crypto Accelerator Cores for Automotive Use Cases Contact Us The automotive-grade CryptoManager Hub (CMH) and CryptoManager Core (CMC) from Rambus are the next-generation of flexible and configurable cryptographic family of accelerator cores comprised of the CMH CH-7xx and CMC CC-7xx designs and are intended […]
CryptoManager Hub (CH-6xx) and CryptoManager Core (CC-6xx) Foundational Crypto Accelerator Cores Contact Us CryptoManager Hub (CMH) and CryptoManager Core (CMC) from Rambus are the next-generation of flexible and configurable cryptographic family of accelerator cores comprised of the CMH CH-6xx and CMC CC-6xx designs and are intended for embedding in customer or Rambus provided Root of […]
The latest PCIe 6.x specification brings groundbreaking advancements in power efficiency and performance optimization. In this technical demonstration, Senior Principal Application Engineer Julien Eydoux showcases two features of Rambus’ PCIe 6.x Controller: L0p mode and FLIT mode operation. Dynamic Power Management The demonstration reveals how L0p mode enables dynamic lane scaling without compromising performance. This […]
Rambus @ DesignCon 2025 Join Rambus for a day of technical sessions at DesignCon on January 29, 2025. Hear from our experts on the technologies that are set to shape the future of data centers and high-performance systems, and discover how our cutting-edge memory, interconnect and security IP enables today’s most challenging computing, edge, automotive […]
The disruption of GenAI over the last few years has forced system architects and hardware designers to rethink data center topologies. While AI model sizes and compute capability are growing exponentially, I/O throughput and memory access are growing linearly. These trends create an unsustainable gap, and it needs to be addressed across the stack starting […]
Security IP Glossary A glossary of Security IP terminology and relevant solutions. a | b | c | d | e | f | g | h | i | j | k | l | m | n | o | p | q | r | s | t | u | v | […]
PCIe 6.2 Switch Contact Us The Rambus PCI Express® (PCIe®) 6.2 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC implementations. It enables the connection of one upstream port and multiple downstream ports as a fully configurable interface subsystem. It is backward compatible to PCIe 5.0.ContactProduct Brief How the PCIe 6.2 Switch […]