At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Found 212 Results
RT-120
https://www.rambus.com/security/root-of-trust/rt-100/RT-120 Root of Trust Foundational security in SoCs and FPGAs for IoT clients and sensors Contact Us Designed to be integrated in power and space-constrained SoCs or FPGAs, the RT-120 Root of Trust (formerly VaultIP) is a FIPS 140-3 compliant hardware core that guards the most sensitive assets on chips and establishes the foundation for […]
Three Top Semiconductor Tech Trends for 2021
https://www.rambus.com/blogs/three-top-semiconductor-tech-trends-for-2021/As a momentous 2020 fades into the history books, 2021 is expected to be a year of growth and evolution for the semiconductor industry across multiple market segments. Firstly, DDR5 DRAM is slated to enter volume production by the end of 2021, with initial deployments targeting hyperscale data centers. Secondly, AI/ML neural networks – which […]
Root of Trust for FPGAs Product Brief
https://go.rambus.com/root-of-trust-for-fpgas-product-brief#new_tabThe Root of Trust for FPGAs is a fully-programmable embedded FIPS 140-2 certified hardware security Root of Trust co-processor integrated in programmable logic. The Root of Trust for FPGAs is a siloed hardware security block, offering secure execution of user applications, tamper detection and protection, secure storage and handling of keys and security assets, resistance […]
Root of Trust for FPGAs
https://www.rambus.com/security/root-of-trust/root-of-trust-for-fpgas/Root of Trust for FPGAs Contact Us FPGAs (Field Programmable Gate Arrays) are widely used in industries such as Defense, Telecommunications, Automotive and AI/ML (Artificial Intelligence/Machine Learning) because of their reconfigurability and flexibility. Whether functioning as the essential building blocks of avionics and spacecraft systems, controlling ADAS (Advanced Driver Assisted Systems) systems, or assisting inference […]
AI Requires Tailored DRAM Solutions: Part 2
https://www.rambus.com/blogs/ai-requires-tailored-dram-solutions-part-2/Written by Rambus Press Frank Ferro, Senior Director Product Management at Rambus, and Shane Rau, Senior Research Executive at IDC, recently hosted a webinar that explores the role of tailored DRAM solutions in advancing artificial intelligence. Part one of this four-part series reviewed a range of topics including the interconnected system landscape, the impact of […]
Rambus Design Summit
https://www.rambus.com/rambus-design-summit-2/October 8, 2020 Register Today Join us for a day of virtual sessions covering the selection and implementation of IP solutions for the data center, 5G/edge and IoT devices including advancing the performance of AI/ML applications. Connect with a community of industry experts and gain insights and practical information for the implementation of their next-generation […]
PCIe 5 Drill-Down with Rambus’ Suresh Andani: Part 3
https://www.rambus.com/blogs/pcie-5-drill-down-with-rambus-suresh-andani-part-3/In part two of this three-part series, Semiconductor Engineering Editor in Chief Ed Sperling and Suresh Andani, Senior Director, Product Marketing and Business Development at Rambus, discussed early market adoption of PCIe 5, as well as the networking environment the specification will support in the data center. In this blog post, Sperling and Andani explore […]
Understanding Anti-Tamper Technology: Part 3
https://www.rambus.com/blogs/understanding-anti-tamper-technology-part-3/Written by Scott Best for the Rambus Blog In part one of this three-part blog series, we discussed the low-cost attacks that target security chips such as protocol and software attacks, brute force glitch attacks, as well environmental attacks. In part two, we took a closer look at attacks executed by more sophisticated adversaries. These […]
PCIe 5 Drill-Down with Rambus’ Suresh Andani: Part 1
https://www.rambus.com/blogs/pcie-5-drill-down-with-rambus-suresh-andani-part-1/Semiconductor Engineering Editor in Chief Ed Sperling recently sat down with Suresh Andani, Senior Director, Product Marketing and Business Development at Rambus, to discuss the evolution of PCIe and its latest iteration: PCIe 5. As Andani notes, PCIe 5 and subsequent iterations of the PCIe standard will continue to be one of the “key interfaces” […]
Memory Systems for AI: Part 6
https://www.rambus.com/blogs/memory-systems-for-ai-part-6/Written by Steven Woo for Rambus Press In part 5 of this series, we discussed the most common memory systems that are used in the highest performance AI applications. These include on-chip memory, high bandwidth memory (HBM) and Graphics DDR SDRAM (GDDR SDRAM). In this blog post, we’ll take an in-depth look at on-chip memory, […]
